Line receiver

Claim 2

An improved line receiver comprising: (A) means for receipt of a differential input voltage wherein such voltage may be algebraically combined with a common mode voltage associated with said differential voltage; (B) input resistors each connected at a first end to said differential input means, for providing a voltage drop; (C) current summing nodes connected to the second end of each input resistor; (D) sinking current mirrors connected to each current summing node so as to absorb current flow from the node to ground; (E) sourcing current mirrors connected to each current summing node so as to provide current to the nodes so that current summing at the nodes is translated into voltage drops that increase the common mode rejection ratio of the line receiver; (F) means for differentially amplifying the differential voltage between the input terminals; and (G) means for receipt of electrical power to energize the receiver; whereby a high common mode rejection ratio with high input impedance operation is achieved that allows for common node voltages to exceed the receiver's power supply voltage as well as to be less than the receiver's ground potential.

Claim 3

An improved line receiver as defined in claim 1, further comprising a constant current source connected to the low potential output of the differential amplifying means.

Claim 4

An improved line receiver as defined in claim 2, wherein the differential amplifying means comprises first and second emitter-coupled transistors (46 and 47), each having a base, an emitter and a collector, and associated collector resistors (52 and 53), each collector resistor connected at one end to the collector of one of the first and second emitter-coupled transistors, and further wherein the line receiver comprises a hysteresis circuit for insuring the fast, snap-action turn-ON of one of said differential amplifier transistors with the simultaneous turn-OFF of the other differential amplifier transistor, and vice-versa, by requiring the differential voltage to exceed a predetermined amount before switching the states of the differential amplifier transistors.

Claim 5

An improved line receiver as defined in claim 3, wherein the hysteresis circuit comprises third and fourth transistors (98 and 99), each having a base, an emitter and a collector, the transistors connected at their bases to the collector resistor-collector junction of the differential amplifier, the third and fourth transistors emitter coupled to each other and connected to a resistor having a second end connected to the means for receipt of electrical power, the collectors of said third and fourth transistors respectively connected to the bases of the differential amplifying means first and second transistors (46 and 47), further wherein the hysteresis circuit comprises fifth and sixth transistors (130 and 132), each having a base, an emitter and a collector, with the bases of the third and fourth transistors connected to the emitters of the fifth and sixth transistors respectively so that upon initial turn-ON of the differential amplifying means first transistor (46), the voltage at the corresponding collector resistor-collector junction causes the emitter of the fifth (130) transistor to have a voltage lower than the emitter voltage of the sixth transistor (132), thus turning ON the corresponding third transistor (198) whose collector current then causes the associated differential amplifying means first transistor (46) to turn-ON more fully until a fully ON state of the differential amplifying means first transistor (46) is achieved, and wherein the turn OFF of the differential amplifying means first transistor (46) causes the third transistor (98) to turn OFF via the emitter voltage of the fifth transistor (130), thereby reducing the base current to the associated differential amplifying means first transistor (46), and further insuring turn-OFF of that transistor, and further so that upon initial turn-ON of the differential amplifying means second transistor (47), the voltage at the corresponding collector resistor-collector junction causes the emitter of the sixth transistor (132) to have a voltage lower than the emitter voltage of the fifth transistor (130), thus turning ON the corresponding fourth transistor (99) whose collector current then causes the associated differential amplifying means second transistor (47) to turn-ON more fully until a fully ON state of the differential amplifying means second transistor (47) is achieved, and wherein the turn OFF of the differential amplifying means second transistor (47) causes the fourth transistor (99) to turn OFF via the emitter voltage of the sixth transistor (132), thereby reducing the base current to the associated differential amplifying means second transistor (47) and further insuring turn-OFF of that transistor.

Claim 6

An improved line receiver as defined in claim 4, wherein the sinking current mirrors comprise emitter-coupled transistors, each having a base, an emitter and a collector, and wherein the sourcing current mirrors comprise emitter-coupled transistors, each having a base, an emitter, and a collector, such that for any increase in current flow by a sinking current mirror a concomitant decrease in current flow is applied by the sourcing current mirror.

Claim 7

An improved line receiver as defined in claim 5, wherein the means for differentially amplifying the differential voltage between the differential input means comprises first and second emitter-coupled transistors, each having a base, an emitter and a collector, said second transistors having their respective bases connected to one of the current summing nodes.

Claim 8

An improved line receiver as defined in claim 6, further wherein the means for differentially amplifying the differential voltage between the input terminals comprises emitter follower transistors (130 and 132), each having a base, an emitter and a collector, the base of each emitter follower transistor respectively connected to the collector of one of the first and second emitter-coupled transistors (46 or 47), and further comprising current sources connected to the emitters of these emitter follower transistors so as to provide a means for pulling down the voltage of the emitter follower transistors emitters, whereby the emitters of these emitter follower transistors can drive emitter coupled logic type circuitry.

Claim 9

An improved line receiver as defined in claim 6, further wherein the means for differentially amplifying the differential voltage between the input terminals comprises emitter follower transistors (130 and 132), each having a base, an emitter and a collector, the base of each emitter follower transistor respectively connected to the collector of one of the first and second emitter-coupled transistors (46 or 47), and further comprising a current mirror (124) with a collector output, the current mirror connected to the emitters of these emitter follower transistors, and further comprising an amplifier output module connected to the collector output of the current mirror (124) so as to current amplify the differential voltage of the first and second emitter-coupled transistors (46 and 47) so as to generate voltage levels compatible to transistor-transistor logic (TTL), integrated injection logic (I 2 L) and integrated Schottky logic (ISL).

Claim 10

An improved line receiver as defined in claim 3, further wherein the means for differentially amplifying the differential voltage between the input terminals comprises emitter follower transistors (130 and 132), each comprising a base, an emitter and a collector, the base of each emitter follower transistor respectively connected to the collector of one of the first and second emitter-coupled transistors (46 or 47), and further comprising current sources connected to the emitters of these emitter follower transistors so as to provide a means for pulling down the emitter voltage of the emitter follower transistors, whereby the emitters of these emitter follower transistors can drive emitter coupled logic (ECL) type circuitry.

Claim 11

An improved line receiver as defined in claim 9, further wherein the means for differentially amplifying the differential voltage between the input terminals comprises emitter follower transistors (130 and 132), each comprising a base, an emitter and a collector, the base of each emitter follower transistor respectively connected to the collector of one of the first and second emitter-coupled transistors (46 or 47), and further comprising a current mirror (124) with a collector output, the current mirror connected to the emitters of these emitter follower transistors, and further comprising an amplifier output module connected to the collector output of the current mirror (124) so as to current amplify the differential voltage of the first and second emitter-coupled transistors (46 and 47) so as to generate voltage levels compatible to transistor-transistor logic (TTL), integrated injection logic (I 2 L) and integrated Schottky logic (ISL).