Asynchronous addressable electronic key telephone system

Claim 2

An asynchronous addressable multiplex system comprising: a master control station having means for formatting and transmitting a series of outgoing message blocks and for receiving and interpreting a series of incoming message blocks; a plurality of satellite stations operatively responsive to the master control station and connected in parallel thereto, the satellite stations including communication means for receiving and interpreting the series of message blocks from the master control station, and for formatting and transmitting a series of message blocks to the master control station, the communication means comprising a computer in each of the plurality of satellite stations, the computer including serial register means for assembling each received and transmitted message block, and a serial input port and a serial output port both connected to the serial register means, each of the plurality of satellite stations further comprising a first clock means for timing the formatting, transmitting and receiving of the series of message blocks, and count reducing means for controlling the reception of and transmission of message blocks by the satellite station, the count reducing means being responsive to the first clock means and providing a clock signal for enabling the serial ports of the computer when message blocks are being transferred, the computer providing direct asynchronous communications for the satellite station with the master control station through the serial ports.

Claim 3

The asynchronous addressable multiplex system of claim 1 wherein the master control station further comprises a second clock means for timing the formatting, transmitting and receiving of the series of message blocks, the first and second clock means being independent of each other.

Claim 4

The asynchronous addressable multiplex system of claim 2 wherein the clock signal provided by the count reducing means is provided at the transfer rate of data comprising the message blocks.

Claim 5

The asynchronous addressable multiplex system of claim 2 wherein the communication means for transmitting data comprising the message blocks further includes a first optical isolator means for causing data provided at the serial output port to be coupled onto a two-wire transmission path interconnecting the satellite station with the master control station.

Claim 6

The asynchronous addressable multiplex system of claim 4 wherein the communication means for receiving data comprising the message blocks further includes a second optical isolator means for causing data received over the two-wire transmission path to be coupled to the serial input port.

Claim 7

The asynchronous addressable multiplex system of claim 5 wherein the communication means in each satellite station further includes control means operative in combination with the count reducing means for controlling the reception of and transmission of message blocks by the satellite station, the control means comprising sensing means for detecting reception of a first data bit of each message block received from the master control station over the two-wire transmission path, the control means enabling the count reducing means upon receipt of this first data bit.

Claim 8

The asynchronous addressable multiplex system of claim 6 wherein the control means further comprises enabling means responsive to the serial register means being loaded with a message block for transmission to the master control station, the enabling means allowing the data from the serial output port to be coupled to the first optical isolator.

Claim 9

The asynchronous addressable multiplex system of claim 2 wherein a first one of the plurality of satellite stations in response to and after reception of a series of incoming message blocks from the master control station responds by transmitting a series of message blocks back to the control station, the control station sending a series of message blocks to another one of the stations during reception of the message blocks from the first satellite station.

Claim 10

An asynchronous addressable multiplex system comprising: a master control station having means for formatting and transmitting a series of outgoing message blocks; a satellite station operatively responsive to the master control station and connected in parallel thereto, the satellite station including communication means for receiving and interpreting the message blocks from the master control station, the communication means comprising a computer in the satellite station, the computer including a serial input port and serial register means for respectively receiving and assembling each message block, the satellite station further comprising a first clock means for timing the formatting and receiving of the series of message blocks, and count reducing means for controlling the reception of message blocks by the satellite station, the count reducing means being responsive to the first clock means and providing a clock signal for enabling the serial input port of the computer when message blocks are being received, the computer providing for direct reception of asynchronous communications for the satellite station from the master control station through the serial input port.

Claim 11

An asynchronous addressable multiplex system comprising: a master control station having means for formatting and transmitting a series of outgoing message blocks; a satellite station operatively responsive to the master control station and connected in parallel thereto, the satellite station including communication means for receiving and interpreting the message blocks from the master control station, the communication means comprising a computer in the satellite station, the computer including a serial input port and serial register means for respectively receiving and assembling each message block, the satellite station further comprising a first clock means for timing the formatting and receiving of the series of message blocks, and count reducing means for controlling the reception of message blocks by the satellite station, the count reducing means being responsive to the first clock means and providing a clock signal for enabling the serial input port of the computer when message blocks are being received, the computer providing for direct reception of asynchronous communications for the satellite station from the master control station through the serial input port.

Claim 12

The asynchronous addressable multiplex system of claim 9 wherein the master control station further comprises a second clock means for timing the formatting and transmitting of the series of message blocks, the first and second clock means being independent of each other.

Claim 13

The asynchronous addressable communication system of claim 10 wherein the clock signal provided by the count reducing means is provided at the reception rate of data comprising the message blocks.

Claim 14

The asynchronous addressable communication system of claim 11 wherein the communication means further includes control means operative in combination with the count reducing means for controlling the reception of message blocks by the satellite station, the control means comprising sensing means for detecting reception of a first data bit of each message block received from the master control station, the control means enabling the count reducing means upon receipt of this first data bit.

Claim 15

An asynchronous addressable multiplex system comprising: a master control station having means for formatting and transmitting a series of outgoing message blocks and for receiving and interpreting a series of incoming message blocks; a plurality of satellite stations operatively reponsive to the master control station and connected in parallel thereto, the satellite stations including communication means for receiving and interpreting the series of message blocks from the master control station, and for formatting and transmitting a series of message blocks to the master control station, the communication means comprising circuitry in each of the plurality of satellite stations, the circuitry including serial register means for assembling each received and transmitted message block, a serial input port and a serial output port both connected to the serial register means, and a central processing unit for interpreting the received message blocks and for formatting the outgoing message blocks, each of the plurality of satellite stations further comprising a first clock means for timing the formatting, transmitting and receiving of the series of message blocks, and count reducing means for controlling the reception of and transmission of message blocks by the satellite station, the count reducing means being responsive to the first clock means and providing a clock signal for enabling the serial ports when message blocks are being transferred, the circuitry providing direct asynchronous communications for the satellite station with the master control station through the serial ports.

Claim 16

An asynchronous addressable multiplex system comprising: a master control station having means for formatting and transmitting a series of outgoing message blocks and for receiving and interpreting a series of incoming message blocks; a plurality of satellite stations operatively reponsive to the master control station and connected in parallel thereto, the satellite stations including communication means for receiving and interpreting the series of message blocks from the master control station, and for formatting and transmitting a series of message blocks to the master control station, the communication means comprising circuitry in each of the plurality of satellite stations, the circuitry including serial register means for assembling each received and transmitted message block, a serial input port and a serial output port both connected to the serial register means, and a central processing unit for interpreting the received message blocks and for formatting the outgoing message blocks, each of the plurality of satellite stations further comprising a first clock means for timing the formatting, transmitting and receiving of the series of message blocks, and count reducing means for controlling the reception of and transmission of message blocks by the satellite station, the count reducing means being responsive to the first clock means and providing a clock signal for enabling the serial ports when message blocks are being transferred, the circuitry providing direct asynchronous communications for the satellite station with the master control station through the serial ports.

Claim 17

The asynchronous addressable multiplex system of claim 13 wherein the master control station further comprises a second clock means for timing the formatting, transmitting and receiving of the series of message blocks, the first and second clock means being independent of each other.

Claim 18

The asynchronous addressable multiplex system of claim 14 wherein the block signal provided by the count reducing means is provided at the transfer rate of data comprising the message blocks.

Claim 19

The asynchronous addressable multiplex system of claim 14 wherein the communication means for transmitting data comprising the message blocks further includes a first optical isolator means for causing data provided at the serial output port to be coupled onto a two-wire transmission path interconnecting the satellite station with the master control station.

Claim 20

The asynchronous addressable multiplex system of claim 16 wherein the communication means for receiving data comprising the message blocks further includes a second optical isolator means for causing data received over the two-wire transmission path to be coupled to the serial input port.

Claim 21

The asynchronous addressable multiplex system of claim 17 wherein the communication means in each satellite station further includes control means operative in combination with the count reducing means for controlling the reception of and transmission of message blocks by the satellite station, the control means comprising sensing means for detecting reception of a first data bit of each message block received from the master control station over the two-wire transmission path, the control means enabling the count reducing means upon receipt of this first data bit.

Claim 22

The asynchronous addressable multiplex system of claim 18 wherein the control means further comprises enabling means responsive to the serial register means being loaded with a message block for transmission to the master control station, the enabling means allowing the data from the serial output port to be coupled to the first optical isolator.

Claim 23

The asynchronous addressable multiplex system of claim 14 wherein a first one of the plurality of satellite stations in response to and after reception of a series of incoming message blocks from the master control station responds by transmitting a series of message blocks back to the control station, the control station sending a series of message blocks to another one of the stations during reception of the message blocks from the first satellite station.

Claim 24

The asynchronous addressable multiplex system of claim 20 wherein the message blocks transmitted by the master control station comprise four eight-bit words and the message blocks transmitted by each satellite station comprise three seven-bit words.