Subscriber line signalling device for use in a telecommunications system

Claim 2

A digital telecommunications system, comprising: a subscriber line interface module for coupling a plurality of independent subscriber paths to a common time division multiplex (TDM) path, the module including a microprocessor responsive to a system control, an interface means connecting the separate subscriber paths to the common TDM path, and a subscriber line signalling device coupled to the interface means and operating under the control of the microprocessor and including: a cyclically permutable codeword generator allocated to each subscriber path for inserting the codeword in serial format into the serial data stream of the path; a cyclically permutable codeword detector allocated to each subscriber path including register means for receiving an incoming serial data stream, means for comparing the data stream with a cyclically permutable codeword stored in register means whereby to recognize a cyclically permutable codeword in the data stream recurring a predetermined number of times; and, a common clock timing means for issuing timing and control signals to all of said detectors and generators of the signalling device for regulating their operation.

Claim 3

A system as claimed in claim 1 wherein said common clock timing means comprises means responsive to the framing pulse signal of the TDM system, and a counter responsive to frame address signals of the TDM system for issuing appropriate timing signals to said detectors and generators.

Claim 4

A system as claimed in claim 1, in which each cyclically permutable codeword detector is arranged to recognise a serial data stream comprising any word repeated (n) times and upon such code being detected a signal is transmitted to said microprocessor.

Claim 5

A system as claimed in claim 1, in which in each cyclically permutable codeword generator a word is loaded by a control interface to a channel address, the word being multiplexed into a serial data stream.

Claim 6

A system as claimed in claim 1 in which the detector comprises a first register means for receiving serial data, second register means for storing a detected cyclically permutable codeword, first comparator means for determining if a cyclically permutable codeword is present in said first register means, second comparator means for comparing the contents of the first register means with the contents of the second register means, wherein if the first and second comparators indicate that a cyclically permutable codeword is valid for (n) word repetitions an interrupt signal is generated and the first register means contents are transferred to the second register means.

Claim 7

A system as claimed in claim 5 wherein said common clock timing means comprises means responsive to the framing pulse signal of the TDM system, and a counter for counting a predetermined number of frame addresses and for issuing a timing signal to each said cyclically permutable detector, each detector including third register means for receiving said timing signal to enable to determine the elapsing of (n) word repetions.

Claim 8

A system as claimed in claim 4, in which the cyclically permutable codeword generator comprises register means for storing said word, and multiplexer means, wherein said word is multiplexed into channels of said serial data stream by frame address strobe signals generated from said clock timing means which is located within the subscriber line interface device and which is driven from a master clock source of the digital telecommunications exchange system.

Claim 9

A system as claimed in claim 7, in which the serial data stream can be transmitted or received from various input and output ports of the device in accordance with the selection of particular command signals.

Claim 10

A system as claimed in claim 8, in which the command signals comprise mode commands which are applied to mode command register means for controlling the operational mode of said plurality of channels and diagnostic commands which are applied to diagnostic command register means for controlling the diagnostic facility of said plurality of channels.

Claim 11

A system as claimed in claim 9, in which self test, bus test, signalling and traffic selections are available for both mode and diagnostic commands.

Claim 12

A system as claimed in claim 10, in which the device is operable in any one fo a plurality of selectable data rates controlled by data rate commands applied to a device control register means.

Claim 13

A system as claimed in claim 11, in which the device control register means has a single-bit alternative setting giving a data rate operation of 16 kbit per second and 32 kbit per second respectively and two further bits whose four possible alternative settings provide four different data rate clock sampling points for employment by the channel detectors.

Claim 14

A subscriber line signalling device for use in a subscriber line interface module of a digital telecommunications system in which the device, being controlled by a microprocessor, is arranged to generate and detect cyclically permutable code words on any of a plurality of independent traffic channel paths to or from the device respectively, each generated cyclically permutable codeword on any one traffic channel path being synchronously coded with respect to any other channel of the plurality of traffic channel paths by clock timing means, in which a cyclically permutable codeword detector is allocated to each channel path, the detector being arranged to recognise a serial data stream comprising any eight-bit word repeated six times and upon such code being detected a signal is transmitted to said microprocessor, in which the detector comprises a first register means for receiving serial data, second register means for storing a detected cyclically permutable codeword, first comparator means for determining if a cyclically permutable codeword is present in said first register means, second comparator means for comparing the contents of the first register means with the contents of the second register means, third register means for storing a frame address count and a true frame address and third comparator means for comparing the frame address count with the true frame address, wherein if the first and second comparators indicate that a cyclically permutable codeword is invalid or old the third register means is loaded with a frame count of minus forty and wherein the third comparator means compares the frame address count with the true frame address such that when a subsequent or new cyclically permutable codeword is valid for forty frame counts an interrupt signal is generated and the first register means contents are transferred to the second register means.

Claim 15

A subscriber line signalling device for use in a subscriber line interface module of a digital telecommunications system in which the device, being controlled by a microprocessor, is arranged to generate and detect cyclically permutable code words on any of a plurality of independent traffic channel paths to or from the device respectively, each generated cyclically permutable codeword on any one traffic channel path being synchronously coded with respect to any other channel of the plurality of traffic channel paths by clock timing means, in which a cyclically permutable codeword detector is allocated to each channel path, the detector being arranged to recognise a serial data stream comprising any eight-bit word repeated six times and upon such code being detected a signal is transmitted to said microprocessor, in which the detector comprises a first register means for receiving serial data, second register means for storing a detected cyclically permutable codeword, first comparator means for determining if a cyclically permutable codeword is present in said first register means, second comparator means for comparing the contents of the first register means with the contents of the second register means, third register means for storing a frame address count and a true frame address and third comparator means for comparing the frame address count with the true frame address, wherein if the first and second comparators indicate that a cyclically permutable codeword is invalid or old the third register means is loaded with a frame count of minus forty and wherein the third comparator means compares the frame address count with the true frame address such that when a subsequent or new cyclically permutable codeword is valid for forty frame counts an interrupt signal is generated and the first register means contents are transferred to the second register means.