Memory control device

Claim 1

An interleave memory system comprising: a plurality of memory blocks; a processor coupled to said plurality of memory blocks for requesting a plurality of memory accesses; an address bus interocnnecting said processor to said memory blocks and enabling transmission of an address containing data to be accessed in said memory block; a write bus interconnecting said processor to said memory blocks and enabling transmission of data to be written into said memory blocks; a single buffer memory means including a first-in, first-out buffer being coupled to said processor via a read bus, said single buffer memory means for temporarily storing data read from said memory blocks before transmitting said data to said processor, said single buffer memory means responding to commands from said processor received via a control line to input data to said processor via said read bus; and a read control bus interconnecting said processor to said single buffer memory means and interconnecting said memory blocks to said single buffer memory means, enabling said processor to transmit signals for the operation of said interleave memory system, said read control bus and said single buffer memory means enabling said processor to request a plurality of memory accesses to a first one of said memory blocks without stopping a preceding memory cycle of said first memory blocks.