US4733372A
Expired / Lapsed
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Semiconductor memory having redundancy
Assignee: Hitachi Ltd
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Filing: 1986-08-06
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Granted: 1988-03-22
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Expires: 2006-08-06
Abstract
Abstract Herein disclosed is a bipolar memory having redundancy, which can be produced with a small area. In this semiconductor memory having a body memory for storing data and a spare memory for relief of fault bit of the body memory, a row is selected by cutting fuses in a decoder. Fundamentally signal lines such as word lines are not provided with fuses. Other parts including a power source and a reference voltage source are provided with fuses without decreasing the operating speed accompanied by only a slight increase in the area.
Inventors
- 👤 Hiroaki Nanbu
- 👤 Kunihiko Yamaguchi
- 👤 Noriyuki Honma
- 👤 Kazuo Kanetani
- 👤 Motoaki Matumoto
- 👤 Kazuhiko Tani
- 👤 Kenichi Ohata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 05:44
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/80; G11C29/83; G11C29/832; G11C29/84
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
158 words
A bipolar memory having redundancy, comprising: a memory array including bipolar memory cells; a redundancy row including at least one row of memory cells; an address buffer made receptive of an address signal; decoder means made receptive of said address signal for selecting said memory array; and redundancy row selecting means including: first and second bipolar transistors having their bases made receptive of said address signal; third and fourth bipolar transistors having their emitter electrodes connected with the emitters of the first and second bipolar transistors and their bases made receptive of a reference voltage; and a current source having fuses connected with said emitter electrodes, respectively, so that a redundancy row selection signal may be outputted from the collectors of said first and third bipolar transistors or said second and fourth bipolar transistors, whereby said fuses are cut so that the selection signal may be outputted when said address signal indicates the address of a fault row.
Claim 2
Dependent Claim
158 words
A bipolar memory having redundancy, comprising: a memory array including bipolar memory cells; a redundancy row including at least one row of memory cells; an address buffer made receptive of an address signal; decoder means made receptive of said address signal for selecting said memory array; and redundancy row selecting means including: first and second bipolar transistors having their bases made receptive of said address signal; third and fourth bipolar transistors having their emitter electrodes connected with the emitters of the first and second bipolar transistors and their bases made receptive of a reference voltage; and a current source having fuses connected with said emitter electrodes, respectively, so that a redundancy row selection signal may be outputted from the collectors of said first and third bipolar transistors or said second and fourth bipolar transistors, whereby said fuses are cut so that the selection signal may be outputted when said address signal indicates the address of a fault row.
Claim 3
Dependent Claim
27 words
A bipolar memory according to claim 1, wherein said current source having fuses further has fifth and sixth bipolar transistors having their bases connected with said fuses.
Claim 4
Dependent Claim
23 words
A bipolar memory according to claim 2, wherein resistors are connected between the bases and emitters of said fifth and sixth bipolar transistors.
Claim 5
Dependent Claim
14 words
A bipolar memory according to claim 3, wherein said fuses are made of poly-silicon.
Claim 6
Dependent Claim
27 words
A bipolar memory according to claim 1, wherein said current source having fuses further has fifth and sixth bipolar transistors having their emitters connected with said fuses.
Claim 7
Dependent Claim
23 words
A bipolar memory according to claim 5, wherein resistors are connected between the bases and emitters of said fifth and sixth bipolar transistors.
Claim 8
Dependent Claim
41 words
A bipolar memory according to claim 1, wherein said current source having fuses further has fifth and sixth bipolar transistors such that fuses are connected in series with resistors between the bases and emitters of said fifth and sixth bipolar transistors.
Claim 9
Dependent Claim
37 words
A bipolar memory according to claim 1, wherein said current source having fuses further has fifth and sixth bipolar transistors having their bases connected with fuses and further their emitters connected with a common internal current source.
Claim 10
Dependent Claim
14 words
A bipolar memory according to claim 8, wherein said fuses are made of poly-silicon.
Claim 11
Dependent Claim
180 words
A bipolar memory having redundancy, comprising: a memory array including bipolar memory cells; a redundancy row including at least one row of memory cells; an address buffer made receptive of an address signal; decoder means made receptive of said address signal for selecting said memory array; and redundancy row selecting means including: first and second bipolar transistors having at least their bases made receptive of said address signal corresponding to an address number; a third bipolar transistor having its emitter electrode connected with the emitters of the first and second bipolar transistors and its base made receptive of a reference voltage; and a current source connected with the emitters of said first, second and third bipolar transistors and the bases or emitters of said first and second or third bipolar transistor are provided with fuses so that the redundancy row selection signal may be outputted from the collectors of said first, second and third bipolar transistors, whereby said fuses are cut so that said selection signal may be outputted when said address signal indicates the address of a fault row.
Claim 12
Dependent Claim
180 words
A bipolar memory having redundancy, comprising: a memory array including bipolar memory cells; a redundancy row including at least one row of memory cells; an address buffer made receptive of an address signal; decoder means made receptive of said address signal for selecting said memory array; and redundancy row selecting means including: first and second bipolar transistors having at least their bases made receptive of said address signal corresponding to an address number; a third bipolar transistor having its emitter electrode connected with the emitters of the first and second bipolar transistors and its base made receptive of a reference voltage; and a current source connected with the emitters of said first, second and third bipolar transistors and the bases or emitters of said first and second or third bipolar transistor are provided with fuses so that the redundancy row selection signal may be outputted from the collectors of said first, second and third bipolar transistors, whereby said fuses are cut so that said selection signal may be outputted when said address signal indicates the address of a fault row.
Claim 13
Dependent Claim
33 words
A bipolar memory according to claim 10, wherein said fuses are made of poly-silicon, and wherein resistors are connected between the bases and emitters of said first and second or third bipolar transistors.
Claim 14
Dependent Claim
17 words
A bipolar memory according to claim 11, wherein said fault row is equipped with voltage stabilization means.
Claim 15
Dependent Claim
25 words
A bipolar memory according to claim 11, wherein said fault row is isolated from the row selection means and is equipped with voltage stabilization means.
Claim 16
Dependent Claim
187 words
A bipolar memory having redundancy, comprising: a memory array including bipolar memory cells; a redundancy row including at least one row of memory cells; an address buffer made receptive of an address signal; decoder means made receptive of said address signal for selecting said memory array; and redundancy row selecting means including: first and second bipolar transistors having their bases made receptive of said address signal; third and fourth bipolar transistors having their emitter electrodes connected with the emitters of the first and second bipolar transistors and their bases made receptive of a reference voltage; and a current source having fuses connected with said emitter electrodes, respectively, so that a redundancy row selection signal may be outputted from the collectors of said first and third bipolar transistors or said second and fourth bipolar transistors, wherein said fault row is isolated from said row selection means, wherein said fault row is equipped with voltage stabilization means, and wherein said fuses are made of poly-silicon, whereby said fuses are cut so that the selection signal may be outputted when said address signal indicates the address of a fault row.7
Claim 17
Dependent Claim
187 words
A bipolar memory having redundancy, comprising: a memory array including bipolar memory cells; a redundancy row including at least one row of memory cells; an address buffer made receptive of an address signal; decoder means made receptive of said address signal for selecting said memory array; and redundancy row selecting means including: first and second bipolar transistors having their bases made receptive of said address signal; third and fourth bipolar transistors having their emitter electrodes connected with the emitters of the first and second bipolar transistors and their bases made receptive of a reference voltage; and a current source having fuses connected with said emitter electrodes, respectively, so that a redundancy row selection signal may be outputted from the collectors of said first and third bipolar transistors or said second and fourth bipolar transistors, wherein said fault row is isolated from said row selection means, wherein said fault row is equipped with voltage stabilization means, and wherein said fuses are made of poly-silicon, whereby said fuses are cut so that the selection signal may be outputted when said address signal indicates the address of a fault row.7
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-03-22 | 1991-09-21 | 1992-03-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-03-22 | 1995-09-21 | 1996-03-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-03-22 | 1999-09-21 | 2000-03-22 | $7700.00 | Window Closed / Lapsed |