US4730346A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for extracting a predetermined bit pattern from a serial bit stream
Assignee: Dallas Semiconductor Corp
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Filing: 1987-02-12
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Granted: 1988-03-08
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Expires: 2007-02-12
Abstract
Abstract An embedded framing bit pattern in a serial bit stream is located by combining the last bit to arrive of the serial bit stream with a predetermined number of prior bits of the serial bit stream which are spaced apart by the pitch of the bits of the framing bit pattern, and this combination of bits is tested to determine if the combination matches part of the framing bit pattern. If a match does not occur, then the bits which were combined together are changed to a bit pattern that will not result in a match when these bits (except for the eldest bit which is disregarded) is combined again with a new bit of the serial bit stream, no matter what the logic state of the new bit. In this manner all of the bits, as they arrive and are combined and tested, will eventually be changed except the bits which are part of the framing bit pattern.
Inventors
- 👤 Ching-Lin Jiang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 13:34
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/0602; H04J3/0605
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
463 words
A method for locating the position of a framing pattern in a serial bit stream wherein each of said framing bits is separated by P-1 bits of data comprising the steps of: (a) after the arrival of [(M-1)×P]+1 bits of said serial bit stream at an input terminal taking M samples P 1 , P 2 , . . . P M of said serial bit stream where P 1 is the last bit of said serial bit stream to have arrived at said input terminal, P 2 is the bit of said serial bit stream which arrived P bits prior to said P 1 bit, and P M is the bit which arrived (M-1)×P bits prior to said P 1 bit; (b) determining if the bit pattern sequence P M . . . P 1 matches any M-bit sequence of the bit pattern formed by concatenating two of said framing patterns; (c) if a match occurs, changing said P 1 , P 2 , . . . P M-1 bit sample to a bit pattern such that the combination of a logic bit X, where logic bit X can be either a logical 1 or a logical 0, and the changed P 1 , P 2 . . . P M-1 bits would not match any sequence of the bit pattern formed by concatenating two of said framing patterns, and if a match does not occur, leaving the bits of said serial bit stream unaffected; (d) upon arrival of the next bit of said serial bit stream at said input terminal taking M samples P 1 , P 2 , . . . P M where P 1 is the last bit of said serial bit stream to have arrived at said input terminal, P 2 is the bit of said serial bit stream which arrived P bits prior to said P 1 bit unless said P 2 bit, when it was in the P 1 position, was previously changed by the process of step (c), and P M is the bit which arrived M-1×P bits prior to said P 1 bit unless said P M bit, when it was in the P 1 , P 2 , . . . P M-2 or P M-1 position, was previously changed by the process of step (c); (e) repeating steps (b) through (d) while counting the number of matches which occur during the arrival of each successive block of said serial bit stream, each block equal to P bits in length; and (f) repeating steps (a) through (e) if said count at the end of any of said blocks is zero, and having identified the position of said framing bits if said count at the end of any of said blocks is one.
Claim 2
Independent Claim
463 words
A method for locating the position of a framing pattern in a serial bit stream wherein each of said framing bits is separated by P-1 bits of data comprising the steps of: (a) after the arrival of [(M-1)×P]+1 bits of said serial bit stream at an input terminal taking M samples P 1 , P 2 , . . . P M of said serial bit stream where P 1 is the last bit of said serial bit stream to have arrived at said input terminal, P 2 is the bit of said serial bit stream which arrived P bits prior to said P 1 bit, and P M is the bit which arrived (M-1)×P bits prior to said P 1 bit; (b) determining if the bit pattern sequence P M . . . P 1 matches any M-bit sequence of the bit pattern formed by concatenating two of said framing patterns; (c) if a match occurs, changing said P 1 , P 2 , . . . P M-1 bit sample to a bit pattern such that the combination of a logic bit X, where logic bit X can be either a logical 1 or a logical 0, and the changed P 1 , P 2 . . . P M-1 bits would not match any sequence of the bit pattern formed by concatenating two of said framing patterns, and if a match does not occur, leaving the bits of said serial bit stream unaffected; (d) upon arrival of the next bit of said serial bit stream at said input terminal taking M samples P 1 , P 2 , . . . P M where P 1 is the last bit of said serial bit stream to have arrived at said input terminal, P 2 is the bit of said serial bit stream which arrived P bits prior to said P 1 bit unless said P 2 bit, when it was in the P 1 position, was previously changed by the process of step (c), and P M is the bit which arrived M-1×P bits prior to said P 1 bit unless said P M bit, when it was in the P 1 , P 2 , . . . P M-2 or P M-1 position, was previously changed by the process of step (c); (e) repeating steps (b) through (d) while counting the number of matches which occur during the arrival of each successive block of said serial bit stream, each block equal to P bits in length; and (f) repeating steps (a) through (e) if said count at the end of any of said blocks is zero, and having identified the position of said framing bits if said count at the end of any of said blocks is one.
Claim 3
Independent Claim
448 words
A method for locating the position of the framing pattern in a T1 serial bit stream encoded according to the ESF standard comprising the steps of: (a) upon the arrival of a bit of said serial bit stream at an input terminal taking 4 samples P 1 , P 2 , P 3 and P 4 of said serial bit stream where P 1 is the last bit to have arrived, P 2 is the bit of said serial bit stream which arrived 772 bits prior to said P 1 bit, P 3 is the bit of said serial bit stream which arrived 772 bits prior to said P 2 bit, and P 4 is the bit which arrived 772 bits prior to said P 3 bit; (b) determining if the bit pattern sequence P 4 , P 3 , P 2 and P 1 matches the any of the bit sequences 0010, 0101, 1011, 0110, 1100 and 1001; (c) if a match occurs, then changing said P 1 , P 2 and P 3 bits to a first logic state, and if a match does not occur, leaving the bits of said serial bit stream unaffected; (d) upon arrival of the next bit of said serial bit stream at said input terminal, taking 4 samples P 1 , P 2 , P 3 and P 4 where P 1 is the last bit of said serial bit stream to have arrived at said input terminal, P 2 is the bit of said serial bit stream which arrived P bits prior to said P 1 bit unless said P 2 bit, when it was in the P 1 position, was previously changed by the process of step (c), P 3 is the bit which arrived 1,544 bits prior to said P 1 bit unless said P 3 bit, when it was in the P 1 or P 2 position, was previously changed by the process of step (c), and P 4 is the bit which arrived 2,316 bits prior to said P 1 bit unless said P 4 bit, when it was in the P 1 , P 2 , or P 3 position, was previously changed by the process of step (c); (e) repeating steps (b) through (d) while counting the number of matches which occur during the arrival of successive blocks of said serial bit stream, each block equal to 772 bits in length; and (f) repeating steps (a) through (e) if said count at the end of any of said blocks is zero, and having identified the position of said framing bits if said count at the end of any of said blocks is one.
Claim 4
Independent Claim
448 words
A method for locating the position of the framing pattern in a T1 serial bit stream encoded according to the ESF standard comprising the steps of: (a) upon the arrival of a bit of said serial bit stream at an input terminal taking 4 samples P 1 , P 2 , P 3 and P 4 of said serial bit stream where P 1 is the last bit to have arrived, P 2 is the bit of said serial bit stream which arrived 772 bits prior to said P 1 bit, P 3 is the bit of said serial bit stream which arrived 772 bits prior to said P 2 bit, and P 4 is the bit which arrived 772 bits prior to said P 3 bit; (b) determining if the bit pattern sequence P 4 , P 3 , P 2 and P 1 matches the any of the bit sequences 0010, 0101, 1011, 0110, 1100 and 1001; (c) if a match occurs, then changing said P 1 , P 2 and P 3 bits to a first logic state, and if a match does not occur, leaving the bits of said serial bit stream unaffected; (d) upon arrival of the next bit of said serial bit stream at said input terminal, taking 4 samples P 1 , P 2 , P 3 and P 4 where P 1 is the last bit of said serial bit stream to have arrived at said input terminal, P 2 is the bit of said serial bit stream which arrived P bits prior to said P 1 bit unless said P 2 bit, when it was in the P 1 position, was previously changed by the process of step (c), P 3 is the bit which arrived 1,544 bits prior to said P 1 bit unless said P 3 bit, when it was in the P 1 or P 2 position, was previously changed by the process of step (c), and P 4 is the bit which arrived 2,316 bits prior to said P 1 bit unless said P 4 bit, when it was in the P 1 , P 2 , or P 3 position, was previously changed by the process of step (c); (e) repeating steps (b) through (d) while counting the number of matches which occur during the arrival of successive blocks of said serial bit stream, each block equal to 772 bits in length; and (f) repeating steps (a) through (e) if said count at the end of any of said blocks is zero, and having identified the position of said framing bits if said count at the end of any of said blocks is one.
Claim 5
Dependent Claim
442 words
Apparatus for locating the position of a bit framing pattern in a serial bit stream wherein each of said framing bits is separated by P-1 bits of data comprising: (a) a serial data input terminal for receiving said serial bit stream; (b) K logic-storage means, each having an input terminal and an output terminal where said input terminal of said first logic-storage means is coupled to said serial data input terminal, said input terminal of said second logic-storage means is coupled to said output terminal of said first logic-storage means, and said rest of said remaining K logic-storage means are similarly connected to form a series circuit in which said Kth logic-storage means is the last circuit of said series circuit, each of said K logic-storage means including means for receiving a logic signal at said input terminal and either setting said logic signal to a first or second logic state or leaving said logic signal unaltered in response to a comparator output signal, for storing said altered or unaltered logic signal sequentially in P storage locations in synchronization with the rate of arrival of said serial bit stream at said serial data input terminal, and for providing at said output terminal the Pth prior altered or unaltered logic signal; (c) comparison means coupled to said serial data input terminal and to said output terminals of said K logic-storage means for determining if the bit of said serial bit stream present at said input terminal in combination with said altered or unaltered logic signals at said output terminals of said first, second, . . . Kth logic-storage means respectively match any (K+1)-bit sequences of the pattern formed by concatenating two of said framing bit patterns and for providing said comparison output signal at an output terminal indicating if a match has occurred or not, said K logic-storage means responding to said comparison output signal by setting each of said logic signals to said first or second logic state such that the combination of a logic bit X, where logic bit X can be either a logical 1 or a logical 0, and said altered logic signals of said first, second, . . . and Kth logic-storage means respectively would not match any sequence of the bit pattern formed by concatenating two of said framing patterns if a match occurs, and if a match does not occur, leaving unaffected said logic signals of said K logic-storage means; and (d) counting means for counting the number of matches which occur during successive blocks of said serial bit stream which arrive at said data input terminal, each of said blocks being P bits in length.
Claim 6
Dependent Claim
442 words
Apparatus for locating the position of a bit framing pattern in a serial bit stream wherein each of said framing bits is separated by P-1 bits of data comprising: (a) a serial data input terminal for receiving said serial bit stream; (b) K logic-storage means, each having an input terminal and an output terminal where said input terminal of said first logic-storage means is coupled to said serial data input terminal, said input terminal of said second logic-storage means is coupled to said output terminal of said first logic-storage means, and said rest of said remaining K logic-storage means are similarly connected to form a series circuit in which said Kth logic-storage means is the last circuit of said series circuit, each of said K logic-storage means including means for receiving a logic signal at said input terminal and either setting said logic signal to a first or second logic state or leaving said logic signal unaltered in response to a comparator output signal, for storing said altered or unaltered logic signal sequentially in P storage locations in synchronization with the rate of arrival of said serial bit stream at said serial data input terminal, and for providing at said output terminal the Pth prior altered or unaltered logic signal; (c) comparison means coupled to said serial data input terminal and to said output terminals of said K logic-storage means for determining if the bit of said serial bit stream present at said input terminal in combination with said altered or unaltered logic signals at said output terminals of said first, second, . . . Kth logic-storage means respectively match any (K+1)-bit sequences of the pattern formed by concatenating two of said framing bit patterns and for providing said comparison output signal at an output terminal indicating if a match has occurred or not, said K logic-storage means responding to said comparison output signal by setting each of said logic signals to said first or second logic state such that the combination of a logic bit X, where logic bit X can be either a logical 1 or a logical 0, and said altered logic signals of said first, second, . . . and Kth logic-storage means respectively would not match any sequence of the bit pattern formed by concatenating two of said framing patterns if a match occurs, and if a match does not occur, leaving unaffected said logic signals of said K logic-storage means; and (d) counting means for counting the number of matches which occur during successive blocks of said serial bit stream which arrive at said data input terminal, each of said blocks being P bits in length.
Claim 7
Dependent Claim
363 words
Apparatus for locating the position of the framing bits in a serial bit stream formed according to the ESF standard comprising: (a) an input terminal for receiving said serial bit stream; (b) a first, second and third logic-storage means, each having an input terminal and an output terminal where said input terminal of said first logic-storage means is coupled to said serial data input terminal, said input terminal of said second logic-storage means is coupled to said output terminal of said first logic-storage means, and said input terminal of said third logic-storage means is coupled to said output terminal of said second logic-storage means, each of said logic-storage means including means for receiving a logic signal at said input terminal and either setting said logic signal to a first logic state or leaving said logic signal unaltered in response to a comparator output signal, for storing said altered or unaltered logic signal sequentially in 772 storage locations in synchronization with the rate of arrival of said serial bit stream at said serial data input terminal, and for providing at said output terminal the 772nd prior altered or unaltered logic signal; (c) comparison means coupled to said serial data input terminal and to said output terminals of said first, second and third logic-storage means for determining if the bit of said serial bit stream present at said input terminal in combination with said altered or unaltered logic signals at said output terminals of said third, second and first logic-storage means respectively match any of the bit patterns 0010, 0101, 1011, 0110, 1100 and 1001 and for providing said comparator output signal at an output terminal indicating if a match has occurred or not, said first, second and third logic-storage means responding to said comparator output signal by setting each of said logic signals to said first logic state if a match occurs, and if a match does not occur, leaving unaffected said logic signals of said logic-storage means; and (d) counting means for counting the number of matches which occur during successive blocks of said serial bit stream which arrive at said data input terminal, each of said blocks being 772 bits in length.
Claim 8
Dependent Claim
363 words
Apparatus for locating the position of the framing bits in a serial bit stream formed according to the ESF standard comprising: (a) an input terminal for receiving said serial bit stream; (b) a first, second and third logic-storage means, each having an input terminal and an output terminal where said input terminal of said first logic-storage means is coupled to said serial data input terminal, said input terminal of said second logic-storage means is coupled to said output terminal of said first logic-storage means, and said input terminal of said third logic-storage means is coupled to said output terminal of said second logic-storage means, each of said logic-storage means including means for receiving a logic signal at said input terminal and either setting said logic signal to a first logic state or leaving said logic signal unaltered in response to a comparator output signal, for storing said altered or unaltered logic signal sequentially in 772 storage locations in synchronization with the rate of arrival of said serial bit stream at said serial data input terminal, and for providing at said output terminal the 772nd prior altered or unaltered logic signal; (c) comparison means coupled to said serial data input terminal and to said output terminals of said first, second and third logic-storage means for determining if the bit of said serial bit stream present at said input terminal in combination with said altered or unaltered logic signals at said output terminals of said third, second and first logic-storage means respectively match any of the bit patterns 0010, 0101, 1011, 0110, 1100 and 1001 and for providing said comparator output signal at an output terminal indicating if a match has occurred or not, said first, second and third logic-storage means responding to said comparator output signal by setting each of said logic signals to said first logic state if a match occurs, and if a match does not occur, leaving unaffected said logic signals of said logic-storage means; and (d) counting means for counting the number of matches which occur during successive blocks of said serial bit stream which arrive at said data input terminal, each of said blocks being 772 bits in length.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-03-08 | 1991-09-07 | 1992-03-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-03-08 | 1995-09-07 | 1996-03-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-03-08 | 1999-09-07 | 2000-03-08 | $7700.00 | Window Closed / Lapsed |