Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
137 words
An arrangement for obtaining a useful recovered signal X(t) for display and/or processing comprising: an analog processor, means for applying an analog signal E(t) to the analog processor, means coupling outputs of the analog processor to a memorization and digitization element, means coupling outputs of the memorization and digitization element to a calculation and test device, which supplies: (a) to a display device or a processing element followed by a display the useful recovered signal X(t) and signals of error function(s) for each analysis period τ as well as synchronization signals and time base signals; and (b) to the analog processor signals for resetting to zero and to a multiplexer synchronization signals, the multiplexer supplying the operating time base signals to the analog processor, to the memorization and digitization element and to the calculation and test device.
Claim 2
Dependent Claim
137 words
An arrangement for obtaining a useful recovered signal X(t) for display and/or processing comprising: an analog processor, means for applying an analog signal E(t) to the analog processor, means coupling outputs of the analog processor to a memorization and digitization element, means coupling outputs of the memorization and digitization element to a calculation and test device, which supplies: (a) to a display device or a processing element followed by a display the useful recovered signal X(t) and signals of error function(s) for each analysis period τ as well as synchronization signals and time base signals; and (b) to the analog processor signals for resetting to zero and to a multiplexer synchronization signals, the multiplexer supplying the operating time base signals to the analog processor, to the memorization and digitization element and to the calculation and test device.
Claim 3
Dependent Claim
110 words
An arrangement for obtaining a useful recovered signal X(t) as claimed in claim 1, characterized in that the analog processor comprises: (a) a processing circuit for processing the analog signal E(t) by functions f k (t); (b) and, a circuit for squaring the analog signal E(t) to provide an output to a signal integrator connected in cascade to a first sampling device; (c) and, two peak detectors responsive to the analog signal E(t) for determining the maximum and the minimum, respectively, of the analog signal E(t) during the analysis period τ, inclusive of the limit values, the said detectors being coupled to a second and a third sampling device, respectively.
Claim 4
Dependent Claim
73 words
An arrangement for obtaining a useful recovered signal X(t) as claimed in claim 2, characterized in that the processing circuit comprises a series arrangement of k elementary filtering stages having outputs A 1 . . . A k and having at said outputs transmittances h 1 (t) . . . h k (t), the outputs A 1 . . . A k being connected respectively to k samplers which supply k output signals.
Claim 5
Dependent Claim
64 words
An arrangement for obtaining a useful recovered signal X(t) as claimed in claim 2, characterized in that the processing circuit comprises k multiplier circuits for multiplying the signal E(t) by the k functions f k (t), a plurality of k respective integration devices connected in cascade with k respective samplers, said samplers having k outputs connected to inputs of the memorization and digitization element.
Claim 6
Dependent Claim
70 words
An arrangement for obtaining a useful recovered signal X(t) as claimed in claim 2, characterized in that the processing circuit comprises k integrators connected in series, the first integrator having a gain -1 and the k th integrator having a gain -k, said integrators each being connected at its output to k respective samplers, the k outputs of the samples being connected to inputs of the memorization and digitization element.
Claim 7
Dependent Claim
24 words
An arrangement for obtaining a useful recovered signal X(t) as claimed in claim 5, characterized in that the variable k is equal to 4.
Claim 8
Dependent Claim
24 words
An arrangement for obtaining a useful recovered signal X(t) as claimed in claim 2, characterized in that the signal integrator comprises an RC circuit.
Claim 9
Dependent Claim
36 words
An arrangement for obtaining a useful recovered signal X(t) as claimed in claim 1, characterized in that the memorization and digitization element comprises an analog memory, an analog-to-digital converter and a digital memory connected in cascade.
Claim 10
Dependent Claim
31 words
An arrangement for obtaining a useful recovered signal X(t) as claimed in claim 1, characterized in that the memorization and digitization element comprises an analog-to-digital converter and a digital memory connected.
Claim 11
Dependent Claim
25 words
An arrangement for obtaining a useful recovered signal X(t) as claimed in claim 8, characterized in that the analog memory is a charge transfer device.
Claim 12
Dependent Claim
14 words
An arrangement as claimed in claim 4 wherein the integration devices comprise RC circuits.
Claim 13
Dependent Claim
13 words
An arrangement as claimed in claim 5 wherein the integrators comprise RC circuits.
Claim 14
Independent Claim
350 words
A device for displaying a useful recovered signal X(t) recovered from an analog signal E(t), with means for forming X(t) per analysis period τ either from samples of a calculated recovered signal S(t) represented in a signal display mode or from minimum and maximum values of the analog signal E(t) represented in an envelope display mode, wherein said device comprises, an analog processor having means provided with k user-chosen functions f k (t), preferably in the form of polynomials, whereby the analog processor comprises means for forming k products E(t)f k (t) and means for forming averages <E(t)f k (t)L22 thereof in the period τ and means for forming averages <E 2 (t)> of the square of E(t), and peak detector means for forming max(SUP) and min(INF) values of E(t), means for sampling said average and said max(SUP) and min(INF) values, an analog memory for storing for every analysis period τ, fitting n times in a period T 1 , said sampled values, an analog-to-digital-converter for digitizing in a subsequent period T 2 the values stored in the analog memory in period T 1 and a digital memory to store the digitized values, a calculation and test device provided with programming means for calculating the recovered signal S(t) from said digitized values, said programming means comprising a first algorithm for inverting a matrix M stored as an array of data in storage means, which matrix M represents calculated values from said user functions, the structure of M being known from a least-squares minimalization procedure, a second algorithm for calculating k coefficients S k by multiplying the inverse matrix M -1 with said k averages <E(t)f k (t)>, a third algorithm for calculating the recovered signal S(t) by multiplying the k coefficients S k with said k functions f k (t), said calculation and test device further comprising decision programming means provided with decision criteria for forming the useful recovered signal(s) X(t) either from S(t) or from said digitized max(SUP) and min(INF) values, and further comprising digital-to-analog converter(s) for reconstructing X(t) to analog signal(s) and a display for displaying the signal(s).
Claim 15
Independent Claim
350 words
A device for displaying a useful recovered signal X(t) recovered from an analog signal E(t), with means for forming X(t) per analysis period τ either from samples of a calculated recovered signal S(t) represented in a signal display mode or from minimum and maximum values of the analog signal E(t) represented in an envelope display mode, wherein said device comprises, an analog processor having means provided with k user-chosen functions f k (t), preferably in the form of polynomials, whereby the analog processor comprises means for forming k products E(t)f k (t) and means for forming averages <E(t)f k (t)L22 thereof in the period τ and means for forming averages <E 2 (t)> of the square of E(t), and peak detector means for forming max(SUP) and min(INF) values of E(t), means for sampling said average and said max(SUP) and min(INF) values, an analog memory for storing for every analysis period τ, fitting n times in a period T 1 , said sampled values, an analog-to-digital-converter for digitizing in a subsequent period T 2 the values stored in the analog memory in period T 1 and a digital memory to store the digitized values, a calculation and test device provided with programming means for calculating the recovered signal S(t) from said digitized values, said programming means comprising a first algorithm for inverting a matrix M stored as an array of data in storage means, which matrix M represents calculated values from said user functions, the structure of M being known from a least-squares minimalization procedure, a second algorithm for calculating k coefficients S k by multiplying the inverse matrix M -1 with said k averages <E(t)f k (t)>, a third algorithm for calculating the recovered signal S(t) by multiplying the k coefficients S k with said k functions f k (t), said calculation and test device further comprising decision programming means provided with decision criteria for forming the useful recovered signal(s) X(t) either from S(t) or from said digitized max(SUP) and min(INF) values, and further comprising digital-to-analog converter(s) for reconstructing X(t) to analog signal(s) and a display for displaying the signal(s).
Claim 16
Dependent Claim
71 words
An arrangement for obtaining a useful recovered signal X(t) as claimed in claim 2 wherein the processing circuit comprises a parallel arrangement of k elementary filtering stages having outputs A 1 . . . A k and having at said outputs transmittances h 1 (t) . . . h k (t), the outputs A 1 . . . A k being connected respectively to k samplers which supply k output signals.
Claim 17
Dependent Claim
44 words
A device as claimed in claim 13, wherein the means for forming k averages <E(t)f k (t)> comprise k multiplier circuits for multiplying E(t) with f k (t) and k integrator circuits for averaging connected in cascade with respective ones of the multiplier circuits.
Claim 18
Dependent Claim
33 words
A device as claimed in claim 13, wherein the means for forming k averages <E(t)f k (t)> comprise a series arrangement of filter devices having respective outputs that yield respective said k averages.
Claim 19
Dependent Claim
33 words
A device as claimed in claim 13, wherein the means for forming k averages <E(t)f k (t)> comprises a parallel arrangement of filter devices having respective outputs that yield respective said k averages.
Claim 20
Dependent Claim
43 words
A device as claimed in claim 17, wherein the filter devices are dimensioned in relation to the k user-chosen functions f k (t) said k averages in consecutive analysis periods τ without the outputs having to be reset after every analysis period τ.
Claim 21
Dependent Claim
52 words
A device as claimed in claim 13, wherein for the choice of user-chosen functions f k (t) of the type f.sub.η (τ)=η(1-t) n-1 the means for forming said k averages <E(t)f k (t)> comprise a series arrangement of integrator circuits with gain -n having respective outputs where said k averages become available.
Claim 22
Dependent Claim
38 words
A device as claimed in claim 13 wherein the decision criteria of the decision programming means comprise at least one error function from the calculated recovered signal S(t) and the analog signal E(t) in the analysis period τ.
Claim 23
Dependent Claim
36 words
A device as claimed in claim 20 wherein the error function determined by the decision programming means is an average quadratic error function <r 2 >=<{E(t)-S(t)} 2 >, wherein r 2 is the quadratic error function.
Claim 24
Dependent Claim
84 words
A device as claimed in claim 20, wherein the error function determined by the decision programming means is a two-valued error function (A,B) of the two respective values A and B, wherein A is the absolute value of {SUP--SUP(S(t))} and B is the absolute value of {INF--INF(S(t))}, wherein SUP(S(t)) is the maximum and INF(S(t)) is the minimum values of S(t) in the analysis period T and wherein SUP and INF are sampled maximum respective minimum signal values of E(t) in the analysis period τ.
Claim 25
Dependent Claim
33 words
A device as claimed in claim 20, wherein the decision programming means comprise means for testing the error functions against predetermined limit values in order to decide for respective envelope or signal mode.
Claim 26
Dependent Claim
131 words
A device as claimed in claim 23, wherein the error functions are the average quadratic error function and the error function (A,B) whereby the decision programming means comprise means for selecting the envelope mode if the average quadratic error function yields a value below a predetermined level B o and further comprise means for selecting the envelope mode if the average quadratic error function yields a value above the predetermined value B o and the error function (A,B) tested against limit values (B 1 , B 2 ) yields values outside the limit values (B 1 , B 2 ) and whereby the decision programming means comprise means for selecting the signal mode for alternative values of the quadratic error function and the error function (A,B) in the analysis period τ.
Claim 27
Dependent Claim
29 words
A device as claimed in claim 24, wherein displayed signals on the display comprise the reconstructed X(t) on the basis of an automatic choice based on the decision criteria.
Claim 28
Dependent Claim
46 words
A device as claimed in claim 23, wherein the displayed signals on the display comprise the error function and the limit values on the basis wherein a manual choice is made for displaying in the respective envelope and signal display mode the useful recovered signal X(t).
Claim 29
Dependent Claim
11 words
A digital oscilloscope comprising a device as claimed in claim 13.