US4726026A
Expired / Lapsed
US
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Fault-tolerant voted output system
Assignee: Triconex Corp
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Filing: 1985-02-08
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Granted: 1988-02-16
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Expires: 2005-02-08
Abstract
Abstract A majority-voted output circuit generates an output parameter which is the majority vote of its input parameters by series-parallel combination of four intermediate switches, each said switch being a Boolean function of the input parameters, and the circuit being arranged so that failure of any one switch does not affect the value of the output parameter. Alternate embodiments are provided which use "don't care" signals to allow the majority vote of less than the full complement of input parameters. The majority-voted output circuit is subjected to testing by stepped transitions of its input parameters (to test for failure of any of the four intermediate switches) and by forcing current flow through predetermined current paths (to test for failure of a particular electrical connection).
Inventors
- 👤 Michael H. Hilford
- 👤 Nathan Tobol
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 17:51
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/18; G06F11/183; G06F11/184; G06F11/185; G06F11/22; G06F11/2205; G06F11/2215; H; H03; H03K; H03K19/00; H03K19/20; H03K19/23
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
140 words
In a majority-vote output circuit for accepting a plurality of input logical values as input parameters, at least one of said input logic values being presented as a plurality of equal valued input parameters, and for generating one output logical value as an output parameter, a method for testing components of the circuit, comprising the steps of: (a) awaiting a transition in input parameters which would generate a change in the output parameter; (b) successively altering each single input parameter of a set input parameters representing a single input logic value from its pre-transition value to its post-transition value; (c) successively checking the resultant output parameter after each input parameter alteration against its expected value; and (d) generating a signal to indicate an error condition if any actual resultant output parameter does not match the corresponding expected resultant output parameter.
Claim 2
Dependent Claim
140 words
In a majority-vote output circuit for accepting a plurality of input logical values as input parameters, at least one of said input logic values being presented as a plurality of equal valued input parameters, and for generating one output logical value as an output parameter, a method for testing components of the circuit, comprising the steps of: (a) awaiting a transition in input parameters which would generate a change in the output parameter; (b) successively altering each single input parameter of a set input parameters representing a single input logic value from its pre-transition value to its post-transition value; (c) successively checking the resultant output parameter after each input parameter alteration against its expected value; and (d) generating a signal to indicate an error condition if any actual resultant output parameter does not match the corresponding expected resultant output parameter.
Claim 3
Dependent Claim
107 words
In a majority-vote output circuit, having a plurality of logic switches, for accepting a plurality of logical values as input parameters and for generating one logical value an an output parameter, a method for testing a current path in the circuit, comprising the steps of: (a) applying control signals to at least one of said logic switches which would force an expected current through a predetermined circuit path; (b) measuring the actual current which passes through the predetermined circuit path; and (c) generating a signal to indicate an error condition if the actual measured current differs from the expected measured current by more than an acceptable limit.
Claim 4
Dependent Claim
107 words
In a majority-vote output circuit, having a plurality of logic switches, for accepting a plurality of logical values as input parameters and for generating one logical value an an output parameter, a method for testing a current path in the circuit, comprising the steps of: (a) applying control signals to at least one of said logic switches which would force an expected current through a predetermined circuit path; (b) measuring the actual current which passes through the predetermined circuit path; and (c) generating a signal to indicate an error condition if the actual measured current differs from the expected measured current by more than an acceptable limit.
Claim 5
Dependent Claim
120 words
In a majority-vote output circuit for accepting a plurality of input logical values as input parameters, at least one of said input logical values being presented as a plurality of equal valued input parameters, and for generating at least one output logical value as an output parameter, a method for testing components of the circuit, comprising the steps of successively altering each single input parameter of a set of input parameters representing a single input logic value from its pre-transition value to its post-transition value; successively checking the resulted output parameter each input parameter alteration against its expected value; and generating a signal to indicate if any actual resultant output parameter does not match the corresponding expected resultant output parameter.
Claim 6
Dependent Claim
120 words
In a majority-vote output circuit for accepting a plurality of input logical values as input parameters, at least one of said input logical values being presented as a plurality of equal valued input parameters, and for generating at least one output logical value as an output parameter, a method for testing components of the circuit, comprising the steps of successively altering each single input parameter of a set of input parameters representing a single input logic value from its pre-transition value to its post-transition value; successively checking the resulted output parameter each input parameter alteration against its expected value; and generating a signal to indicate if any actual resultant output parameter does not match the corresponding expected resultant output parameter.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-02-15 | 1991-08-17 | 1992-02-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-02-15 | 1995-08-17 | 1996-02-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-02-15 | 1999-08-17 | 2000-02-16 | $7700.00 | Window Closed / Lapsed |