US4725882A
Expired / Lapsed
US
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Scrambled video signal processor
Assignee: Toshiba Corp
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Filing: 1986-09-29
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Granted: 1988-02-16
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Expires: 2006-09-29
Abstract
Abstract A scrambled video signal processor comprises an amplifier for outputting a noninverted video signal and an inverted video signal, a timing pulse controller for generating first and second timing pulses at a pedestal position in an arbitrary horizontal synchronous signal period of the video signal, and a third timing pulse in an arbitrary video period of the video signal, first and second pedestal clampers for receiving one of the noninverted and inverted video signals from the amplifier and clamping a pedestal level of the arbitrary horizontal synchronous signal period, an offset level controller for receiving the first timing pulse, for DC-restoring to a first level the pedestal position of the horizontal synchronous signal period of the noninverted video signal, and for DC-restoring to a second level, which is different from the first level, the pedestal position of the horizontal synchronous signal period of the inverted signal, a pedestal level controller for DC-restoring to a third level of the other pedestal position of the horizontal synchronous signal period of the inverted video signal in response to the second timing pulse, and a first switch which is switched to select one of the first and second pedestal clampers in response to the third timing pulse.
Inventors
- 👤 Yoichiro Sato
- 👤 Koichi Minemura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 06:21
CPC Classifications
H; H04; H04N; H04N7/00; H04N7/16; H04N7/167; H04N7/171; H04N7/1716
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
330 words
A scrambled video signal processor comprising: circuit means for receiving a scrambled video signal and outputting a noninverted video signal from a first output section thereof and an inverted video signal from a second output section thereof; timing pulse control means for generating a first timing pulse at a pedestal position in an arbitrary horizontal synchronous signal period of the video signal, a second timing pulse at another pedestal position of the arbitrary horizontal synchronous signal period, a third timing pulse in an arbitrary video period of the video signal, and a fourth offset timing pulse; first pedestal clamp means for receiving the noninverted video signal from said first output section in said circuit means and clamping a pedestal level of the arbitrary horizontal synchronous signal period; second pedestal clamp means for receiving the inverted video signal from said second output section in said circuit means and clamping a pedestal level of the arbitrary horizontal synchronous signal period; offset level control means for receiving the first timing pulse from said timing pulse control means and for DC-restoring to a first level the pedestal position of the horizontal synchronous signal period of the inverted video signal appearing at said first output section in said circuit means and for DC-restoring to a second level the pedestal position of the horizontal synchronous signal period of the noninverted signal appearing at said second output section in said circuit means, the second level being different from the first level; pedestal level control means, connected to one of said first and second pedestal clamp means, for DC-restoring to a third level, different from the first and second levels, the other pedestal position of the horizontal synchronous signal period of the noninverted video signal in response to the second timing pulse from said timing pulse control means; and first switching means switched to select said second pedestal clamp means in response to the third timing pulse from said timing control means, for outputting a descrambled video signal.
Claim 2
Dependent Claim
330 words
A scrambled video signal processor comprising: circuit means for receiving a scrambled video signal and outputting a noninverted video signal from a first output section thereof and an inverted video signal from a second output section thereof; timing pulse control means for generating a first timing pulse at a pedestal position in an arbitrary horizontal synchronous signal period of the video signal, a second timing pulse at another pedestal position of the arbitrary horizontal synchronous signal period, a third timing pulse in an arbitrary video period of the video signal, and a fourth offset timing pulse; first pedestal clamp means for receiving the noninverted video signal from said first output section in said circuit means and clamping a pedestal level of the arbitrary horizontal synchronous signal period; second pedestal clamp means for receiving the inverted video signal from said second output section in said circuit means and clamping a pedestal level of the arbitrary horizontal synchronous signal period; offset level control means for receiving the first timing pulse from said timing pulse control means and for DC-restoring to a first level the pedestal position of the horizontal synchronous signal period of the inverted video signal appearing at said first output section in said circuit means and for DC-restoring to a second level the pedestal position of the horizontal synchronous signal period of the noninverted signal appearing at said second output section in said circuit means, the second level being different from the first level; pedestal level control means, connected to one of said first and second pedestal clamp means, for DC-restoring to a third level, different from the first and second levels, the other pedestal position of the horizontal synchronous signal period of the noninverted video signal in response to the second timing pulse from said timing pulse control means; and first switching means switched to select said second pedestal clamp means in response to the third timing pulse from said timing control means, for outputting a descrambled video signal.
Claim 3
Dependent Claim
14 words
A processor according to claim 1, wherein said circuit means comprises a differential amplifier.
Claim 4
Dependent Claim
141 words
A processor according to claim 1, wherein said timing pulse control means comprises: a control circuit for generating first, second and third control signals synchronized with a position data predetermined on the basis of horizontal and vertical synchronous signals said first, second and third control signals being output on the basis of the position data sampled by a data sampling circuit in response to the timing signals synchronized with the predetermined position data, an offset pedestal timing circuit for receiving the first control signal and outputting the first timing pulse to said offset level control means, a pedestal clamp timing circuit for receiving the second control signal and outputting the second timing pulse to said pedestal level control means, and an inverter timing circuit for receiving the third control signal and outputting the third timing pulse to said first switching means.
Claim 5
Dependent Claim
192 words
A processor according to claim 1, wherein said timing pulse control means comprises: a reset timing circuit for receiving horizontal and vertical synchronous signals from a synchronous signal separation circuit, supplying a data sampling timing signal to a data sampling circuit, and causing said data sampling circuit to supply the position data; a decoder for receiving the position data and decoding the position data by communication with a microcomputer; a first pulse generator for receiving the position data decoded by said decoder and said microcomputer and a reset signal from said reset timing circuit and generating a fourth timing pulse; a second pulse generator for receiving the position data decoded by said decoder and said microcomputer and a reset signal from said reset timing circuit and generating said third timing pulse; a third pulse generator for receiving the reset signal and generating a pedestal timing signal including an offset pedestal timing signal and a pedestal clamp signal; and a logic circuit for receiving the pedestal timing signal from said third pulse generator and the fourth timing pulse from said first pulse generator to separate and output the first and second timing pulses.
Claim 6
Dependent Claim
72 words
A processor according to claim 1, wherein said first and second pedestal clamp means each comprise: transistors for receiving the noninverted and inverted video signals from said first and second output sections in said circuit means; coupling capacitors inserted between said switch means and outputs of said transistors; emitter resistors connected to emitters of said transistors; and color burst trap circuits connected to said outputs of said transistors through said coupling capacitors.
Claim 7
Dependent Claim
21 words
A processor according to claim 5, wherein said color burst trap circuits respectively comprise parallel circuits of capacitors, resistors, and coils.
Claim 8
Dependent Claim
143 words
A processor acccording to claim 1, wherein said offset level control means comprises: second and third switching means which are turned on in response to the first timing pulse from said timing pulse control means; a first capacitor for DC-restoring to the first level the pedestal position in the horizontal synchronous signal period of the noninverted video signal appearing at said first output section in said circuit means upon closing of said second switching means; arithmetic means for receiving an output from said first capacitor and generating an output corresponding to the first level; and a second capacitor for DC-restoring, to the second level corresponding to the output from said arithmetic means, the pedestal position in the horizontal synchronous signal period of the inverted video signal appearing at said second output section in said circuit means upon closing of said third switching means.
Claim 9
Dependent Claim
70 words
A processor according to claim 7, wherein said arithmetic means comprises: an operational amplifier, a noninverting input terminal of which is connected to said first capacitor and an output terminal of which is fed back to an inverting input terminal thereof; and a variable resistor inserted between the output terminal of said operational amplifier and ground, said variable resistor being provided with a sliding contact connected to said second capacitor.
Claim 10
Dependent Claim
61 words
A processor according to claim 7, wherein said pedestal level control means comprises: fourth switching means which is turned on in response to the first control signal from said offset pedestal timing circuit; and a third capacitor for DC-restoring to the third level the noninverted or inverted video signal appearing at said first or second output section in said circuit means.
Claim 11
Dependent Claim
17 words
A processor according to claims 9, wherein said second, third, and fourth switching means comprise semiconductor elements.
Claim 12
Dependent Claim
15 words
A processor according to claim 1, wherein said first switching means comprises an analog switch.
Claim 13
Dependent Claim
108 words
A processor according to claim 3, wherein said first switching means further comprises a synchronous signal offset releasing means for restoring to a previous level the level of a synchronous signal which is obtained by offsetting the video signal output from the pedestal clamp means selected in response to a fourth timing pulse, thus outputting said descrambled video signal; and wherein said timing pulse control means further comprises a synchronous signal offset timing circuit which receives a fourth control signal output from said control circuit in synchronism with said position data, and outputs said fourth timing pulse indicative of a timing with which to offset the synchronous signal.
References Cited (Backward Citations)
US3396232A
Cited
US3924059A
Cited
US4075660A
Cited
US4222068A
Cited
US4336553A
Cited
US4340906A
Cited
US4598318A
Cited
US4651205A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-02-15 | 1991-08-17 | 1992-02-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-02-15 | 1995-08-17 | 1996-02-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-02-15 | 1999-08-17 | 2000-02-16 | $7700.00 | Window Closed / Lapsed |