Circuit arrangement for identifying specific bit patterns, particularly bit patterns forming synchronization signals and check loop signals and appearing as serial binary signals

Claim 1

A circuit arrangement for identifying specific bit patterns, including synchronization signals and check loop signals, in binary signals appearing serially on a plurality of signal lines, comprising: a plurality of clock-controlled flip-flops each connected to a respective signal line; a plurality of signal receiving circuits each connected to a respective flip-flop and each comprising first memory means connected to the respective flip-flop, a counter including a counting input connected to the respective flip-flop and a setting input and an output, first and second signal transfer circuits connected to said first memory means for receiving the bits clocked in via said flip-flop, a buffer connected to said second signal transfer circuit, and a gate including an output connected to said setting input and a plurality of address inputs; a bus system; and comparison means for comparing received bit patterns with at least one predetermined bit pattern, said comparison means comprising second memory means connected to said bus system and storing said at least one predetermined bit pattern and a clock-controlled microprocessor connected to said bus system and operated to selectively address a signal line by addressing the respective gate of the respective signal receiving circuit and set the respective counter, said first and second signal transfer circuits and said buffer connected to said bus system and addressed and controlled by said microprocessor for bit pattern transfer, and said output of said counter connected to said second signal transfer circuit to enable bit pattern transfer to said buffer when said counter reaches a predetermined count.