Camera information transmission system

Claim 1

A microprocessor based camera information transmission system capable of electrically transmitting various information on a plurality of different camera accessories from the camera accessories to the camera body with which said accessories are usable for controlling the operation of the camera in conjunction with a given one of said accessories, said plurality of different accessories comprising accessory information which is different in content and quantity for different camera accessories in said plurality, each of said accessories comprising means for transmitting an information identification code to said camera body for identifying the content and quantity of accessory information corresponding thereto and means for sequentially and serially providing said identified accessory information to said camera body, said camera body comprising a microprocessor comprising data register means and means for detecting said identification code, said transmitted accessory information comprising preset information electrically transmitted to said microprocessor in accordance with said detected identification code, said means for detecting said identification code comprising flip flop means connected to a serial data read output of said microprocessor for being set thereby, said flip flop providing one input to an AND gate whose output comprises a clock signal for said corresponding accessory and for a data input register in said camera body, said data input register being capable of receiving said accessory information and said identification code from said corresponding accessory when said accessory is electrically connected to said camera body, said AND gate having another input connected to a clock signal output of said microprocessor, said data input register being connected to a data bus input to said microprocessor, the setting of said flip flop causing a fetch to be made from said data bus input to said microprocessor for detecting said identification code of said corresponding accessory provided to said data input shift register, said detected identification code setting the quantity content of said microprocessor data register means for said corresponding accessory, said corresponding accessory comprising a condition responsive output gate array and an input shift register decoder means, said input shift register decoder means being electrically connected to said AND gate clock output and said output gate array being connected between said input shift register decoder means output and said data input register input for selectively providing said accessory information thereto in response to said decoder clock output for sequentially and serially providing a synchronized serial bit pattern to said microprocessor in accordance with said detected accessory identification code.