Magnetoresistive random access cross-tie memory architecture and signal processing system

Claim 2

A magnetoresistive random access cross-tie memory array comprising: (a) an insulating subtrate; (b) a plurality of spaced columns of thin film magnetoresistive material disposed upon said substrate, which thin film columns are symmetrically patterned and shaped to provide only two stable magnetic domain states at spaced memory elements which form an X-Y array of spaced apart memory elements which are magnetically addressable to one of two possible stable states, and wherein a single binary digital bit is written and stored at four memory elements which are defined on four spaced adjacent columns of magnetoresistive material, with one memory element of the four being located along each of the four columns of magnetoresistive material; (c) row conductors aligned over row aligned pairs of memory elements, with two of the four memory elements aligned under a first row conductor, and the other two memory elements are aligned under a second row conductor; (d) serpentine shaped column conductors having columnar extending portions interconnecting row aligned extending portions arranged so that adjacent row extending portions conduct current in opposed directions over row adjacent memory elements whereby a single binary digit can be stored in complementary fashion in a pair of adjacent memory elements, and wherein all four memory elements for a single binary digital bit are aligned under a single serpentine column conductor, with the two memory elements aligned under the first row conductor aligned under a first row conductor aligned portion of the serpentine column conductor, and the other two memory elements aligned under the second row conductor are aligned under a second row conductor aligned portion of the serpentine column, with the signals in the first and second row conductor aligned portions of the serpentine columns being complementary signals.

Claim 3

The magnetoresistive random access cross-tie memory array system set forth in claim 1, wherein the single binary digit is written and stored at the four memory elements by applying a half address signal to the serpentine column, while simultaneously applying complementary half address signals to the first and second row conductors.

Claim 4

The magnetoresistive random access cross-tie memory array system set forth in claim 1, wherein the single binary digit is read out by applying a read signal to the selected column of magnetoresistive material while applying a half address read signal to the selected row conductor to affect a change of resistance at the selected memory element as a function of the applied magnetic field, which magnetoresistive effect is detectable to identify one of two stable magnetic domain states which represent the binary data.

Claim 5

A magnetoresistive random access cross-tie memory array system comprising: (a) a plurality of spaced columns of thin film of magnetoresistive material disposed upon a substrate and shaped to exhibit only two stable magnetic domain states, which thin film columns are symmetrically patterned to provide an X-Y array of spaced apart memory elements which are magnetically addressable to one of two possible stable states and wherein a single binary digital bit is written and stored at four memory elements which are defined on four spaced adjacent columns of magnetoresistive material, with one memory element of the four being located along each of the four columns of magnetoresistive material; (b) row conductors aligned over row aligned pairs of memory elements with two of the four memory elements aligned under a first row conductor, and the other two memory elements are aligned under a second row conductor; (c) serpentine shaped column conductors having columnar extending portions interconnecting row aligned extending portions arranged so that adjacent row aligned extending portions conduct current in opposed directions over row aligned adjacent memory elements, and wherein all four memory elements for a single binary digital bit are aligned under a single serpentine column conductor, with the two memory elements aligned under the first row conductor aligned under a first row conductor aligned portion of the serpentine column conductor, and the other two memory elements aligned under the second row conductor are aligned under a second row conductor aligned portion of the serpentine column, with the signals in the first and second row conductor aligned portions of the serpentine columns being complementary signals; (d) digital signal writing means connectable to the row and column conductors whereby a single binary digit can be stored in complementary fashion in (a pair of adjacent) the four (cells) elements; (e) means connectable to the thin film columns when the stored binary data is to read out of memory; (f) digital sequential read signal means connectable to the row conductors, which read signal produces a magnetoresistive response in the memory elements which response is indicative of the respective stable states written into the memory elements; (g) memory array read-out signal processor means for differentially processing the magnetoresistive response induced voltage increment from the complementary memory cells.

Claim 6

A magnetoresistive random access cross-tie memory array system comprising: (a) a plurality of spaced columns of thin film of magnetoresistive material disposed upon a substrate and shaped to exhibit only two stable magnetic domain states, which thin film columns are symmetrically patterned to provide an X-Y array of spaced apart memory elements which are magnetically addressable to one of two possible stable states and wherein a single binary digital bit is written and stored at four memory elements which are defined on four spaced adjacent columns of magnetoresistive material, with one memory element of the four being located along each of the four columns of magnetoresistive material; (b) row conductors aligned over row aligned pairs of memory elements with two of the four memory elements aligned under a first row conductor, and the other two memory elements are aligned under a second row conductor; (c) serpentine shaped column conductors having columnar extending portions interconnecting row aligned extending portions arranged so that adjacent row aligned extending portions conduct current in opposed directions over row aligned adjacent memory elements, and wherein all four memory elements for a single binary digital bit are aligned under a single serpentine column conductor, with the two memory elements aligned under the first row conductor aligned under a first row conductor aligned portion of the serpentine column conductor, and the other two memory elements aligned under the second row conductor are aligned under a second row conductor aligned portion of the serpentine column, with the signals in the first and second row conductor aligned portions of the serpentine columns being complementary signals; (d) digital signal writing means connectable to the row and column conductors whereby a single binary digit can be stored in complementary fashion in (a pair of adjacent) the four (cells) elements; (e) means connectable to the thin film columns when the stored binary data is to read out of memory; (f) digital sequential read signal means connectable to the row conductors, which read signal produces a magnetoresistive response in the memory elements which response is indicative of the respective stable states written into the memory elements; (g) memory array read-out signal processor means for differentially processing the magnetoresistive response induced voltage increment from the complementary memory cells.