US4722070A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multiple oscillation switching circuit
Assignee: Texas Instruments Inc
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Filing: 1986-07-03
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Granted: 1988-01-26
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Expires: 2006-07-03
Abstract
Abstract A multiple oscillator switching circuit for a digital processing system that includes a central processing unit having a first internal timing cycle and connected to a plurality of peripheral devices, each peripheral device having an independent internal timing cycle. The central processing unit is further connected to an oscillator switching circuit. The oscillator switching circuit includes several oscillators. Each oscillator has an output consisting of an independent internal frequency. A selected number of these oscillators have independent internal frequencies that correspond to the internal timing of the peripheral devices. These oscillator switching circuits are further connected to the central processing unit and to the output of each of the oscillators for providing a single oscillator output to the central processing unit in response to an output from the central processing unit. This capability allows the central processing unit to control its internal timing in order to slow the central processing unit to a timing cycle that will match the timing cycle of the peripheral devices. In addition the oscillator switching circuits provide an impedance matching between the output of the oscillators and the input to the central processing unit.
Inventors
- 👤 Thomas A. Dye
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 04:02
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/12; G06F1/08
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
296 words
A digital processing system comprising: a plurality of peripheral devices, each peripheral device having an independent internal timing cycle; a plurality of oscillator means, each having an output consisting of an independent internal frequency corresponding to the internal timing of at least one peripheral device; a central processing unit connected to said plurality of peripheral devices, having at least one clock signal input, a first internal timing cycle corresponding to the frequency of the signal received on said at least one clock signal input, and at least one oscillator selection output; an oscillator switching circuit connected to said central processing unit and the output of each of said oscillator means for providing a single oscillator output to said at least one clock signal input of said central processing unit in response to said oscillation selection output from the central processing unit so as to conform the internal timing of said central processing unit to that of at least one of said peripheral devices; said at least one oscillator selection output includes a first oscillator selection output for choosing between a primary oscillator signal and said plurality of oscillator means and at least one second oscillator selection output for selecting a secondary oscillator signal from among said plurality of oscillator means; and said oscillator switching circuit includes a primary oscillator connected to said at least one clock signal input for generating said primary oscillator signal, primary switching means connected to said first oscillator selection output for enabling or disabling said primary oscillator and secondary switching means connected to said at least one second oscillator selection output for coupling the output of one of said plurality of oscillator means to said at least one clock signal input in accordance with said at least one second oscillation selection output.
Claim 2
Dependent Claim
296 words
A digital processing system comprising: a plurality of peripheral devices, each peripheral device having an independent internal timing cycle; a plurality of oscillator means, each having an output consisting of an independent internal frequency corresponding to the internal timing of at least one peripheral device; a central processing unit connected to said plurality of peripheral devices, having at least one clock signal input, a first internal timing cycle corresponding to the frequency of the signal received on said at least one clock signal input, and at least one oscillator selection output; an oscillator switching circuit connected to said central processing unit and the output of each of said oscillator means for providing a single oscillator output to said at least one clock signal input of said central processing unit in response to said oscillation selection output from the central processing unit so as to conform the internal timing of said central processing unit to that of at least one of said peripheral devices; said at least one oscillator selection output includes a first oscillator selection output for choosing between a primary oscillator signal and said plurality of oscillator means and at least one second oscillator selection output for selecting a secondary oscillator signal from among said plurality of oscillator means; and said oscillator switching circuit includes a primary oscillator connected to said at least one clock signal input for generating said primary oscillator signal, primary switching means connected to said first oscillator selection output for enabling or disabling said primary oscillator and secondary switching means connected to said at least one second oscillator selection output for coupling the output of one of said plurality of oscillator means to said at least one clock signal input in accordance with said at least one second oscillation selection output.
Claim 3
Dependent Claim
17 words
A digital processing system as claimed in claim 1, wherein: said primary oscillator comprises a crystal oscillator.
Claim 4
Dependent Claim
260 words
A digital processing system comprising: a central processing unit connected to a plurality of peripheral devices, having at least one clock signal input, a first internal timing cycle corresponding to the frequency of the signal received on said at least one clock signal input, and at least one oscillator selection output; an oscillator switching circuit connected to said central processing unit having a plurality of oscillator input lines, each for receiving an oscillator signal, for providing a single oscillator output to said at least one clock signal input of said central processing unit in response to said oscillation selection output from the central processing unit so as to conform the internal timing of said central processing unit to that of at least one of said peripheral devices; said at least one oscillator selection output includes a first oscillator selection output for choosing between a primary oscillator signal and said plurality of oscillator means and at least one second oscillator selection output for selecting a secondary oscillator signal from among said plurality of oscillator means; and said oscillator switching circuit includes a primary oscillator connected to said at least one clock signal input for generating said primary oscillator signal, primary switching means connected to said first oscillator selection output for enabling or disabling said primary oscillator and secondary switching means connected to said at least one second oscillator selection output for coupling the output of one of said plurality of oscillator means to said at least one clock signal input in accordance with said at least one second oscillation selection output.
Claim 5
Dependent Claim
260 words
A digital processing system comprising: a central processing unit connected to a plurality of peripheral devices, having at least one clock signal input, a first internal timing cycle corresponding to the frequency of the signal received on said at least one clock signal input, and at least one oscillator selection output; an oscillator switching circuit connected to said central processing unit having a plurality of oscillator input lines, each for receiving an oscillator signal, for providing a single oscillator output to said at least one clock signal input of said central processing unit in response to said oscillation selection output from the central processing unit so as to conform the internal timing of said central processing unit to that of at least one of said peripheral devices; said at least one oscillator selection output includes a first oscillator selection output for choosing between a primary oscillator signal and said plurality of oscillator means and at least one second oscillator selection output for selecting a secondary oscillator signal from among said plurality of oscillator means; and said oscillator switching circuit includes a primary oscillator connected to said at least one clock signal input for generating said primary oscillator signal, primary switching means connected to said first oscillator selection output for enabling or disabling said primary oscillator and secondary switching means connected to said at least one second oscillator selection output for coupling the output of one of said plurality of oscillator means to said at least one clock signal input in accordance with said at least one second oscillation selection output.
Claim 6
Dependent Claim
202 words
A digital processing system as claimed in claim 3, wherein: said at least one clock signal input includes a first clock signal input and a second clock signal input; said primary oscillator includes a crystal having first and second terminals connected to said first and second clock signal inputs of said central processing unit, respectively; said primary switching means comprises a first tristate buffer having an input for receiving said selected secondary oscillator signal, an output AC coupled to said first terminal of said crystal and a control input connected to said first oscillator selection output, and a second tristate buffer having an input connected to ground, an output connected to the said second terminal of said crystal and a control input connected to said first oscillator selection ouput, whereby when said first oscillator selection output is in a first state the outputs of said first and second tristate buffers is a high impedance enabling said crystal to oscillate and when said first oscillator selection output is in a second state said second tristate buffer disables oscillation of said crystal and said first tristate buffer applies said selected secondary oscillator signal to said first clock signal input of said central processing unit.
Claim 7
Dependent Claim
102 words
A digital processing system as claimed in claim 4, wherein: said secondary switching means includes a plurality of third tristate buffers, each having an input connected to a corresponding one of said oscillator input lines, an output connected to said input of said first tristate buffer and a control input, and a third buffer selection means connected to said control input of each of said third tristate buffers for enabling only one of said third tristate buffers to pass the oscillator signal received on its corresponding oscillator input line, whereby the outputs of the other third tristate buffers is a high impedance.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-01-25 | 1991-07-27 | 1992-01-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-01-25 | 1995-07-27 | 1996-01-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-01-25 | 1999-07-27 | 2000-01-26 | $7700.00 | Window Closed / Lapsed |