US4718057A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Streamlined digital signal processor
Assignee: Advanced Micro Devices Inc
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Filing: 1985-08-30
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Granted: 1988-01-05
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Expires: 2005-08-30
Abstract
Abstract An all-digital signal processor (DSP) is disclosed which performs pulse code modulation (PCM) coding and decoding (CODEC) filter operations for both received and transmitted signals, among other functions. A user can access various programmable registers via the microprocessor to specify parameters used in the execution of programs by the DSP. Two 19-bit wide bidirectional data busses are provided for time-division multiplexed communication between various elements, which include a random access memory (RAM), an arithmetic-logic unit (ALU), and an interface to a receive-side analog-to-digital (A/D) converter and a transmit-side digital-to-analog (D/A) converter. A programmed logic array (PLA) executes microcode which controls the processing of signals by the ALU section. A variety of other operations can be performed under control of the PLA such as generation of dual-tone multi-frequency (DTMF) signals commonly used in telecommunications. The architecture of the DSP provides a number of user-accessible registers for the storage of parameters and coefficients used in the generation of the DTMF signals, in the CODEC filtering, and in the compression and expansion of signals. The design of the general-purpose DSP is readily expandible to accomodate additional circuit elements and/or more signals to be processed in parallel.
Inventors
- 👤 P. Venkitakrishnan
- 👤 Gururaj Singh
- 👤 Ronald C. Laugesen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 09:11
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/78; G06F15/7828; G06F15/7832; H; H04; H04M; H04M1/00; H04M1/253; H04Q; H04Q1/00; H04Q1/18; H04Q1/30; H04Q1/44; H04Q1/444; H04Q1/45; H04Q1/457; H04Q1/4575; H04Q11/00; H04Q11/04; H04Q11/0428; H04Q2213/00; H04Q2213/13034; H04Q2213/13103; H04Q2213/13106; H04Q2213/13107; H04Q2213/1319; H04Q2213/13216; H04Q2213/13292; H04Q2213/1332; H04Q2213/13396; H04Q2213/13405
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
137 words
A processor connected to a source of time-division multiplexed (TDM) digital signals, a destination of TDM digital signals and a dual PCM channel, having a central control responsive to signals received from an external device, said central control cyclically processes instructions and generates control signals therefrom, said processor further comprising: an arithmetic logic unit (ALU) responsive to said control signals; a first bidirectional data bus connected to said ALU and said source of TDM digital signals; and a second bidirectional data bus connected to said ALU and said PCM channel; whereby said TDM signals are received from said source by said ALU via said first data bus and processed by said ALU in response to said signals received from said external device and transmitted by said ALU via said second data bus over said dual PCM channel.
Claim 2
Dependent Claim
137 words
A processor connected to a source of time-division multiplexed (TDM) digital signals, a destination of TDM digital signals and a dual PCM channel, having a central control responsive to signals received from an external device, said central control cyclically processes instructions and generates control signals therefrom, said processor further comprising: an arithmetic logic unit (ALU) responsive to said control signals; a first bidirectional data bus connected to said ALU and said source of TDM digital signals; and a second bidirectional data bus connected to said ALU and said PCM channel; whereby said TDM signals are received from said source by said ALU via said first data bus and processed by said ALU in response to said signals received from said external device and transmitted by said ALU via said second data bus over said dual PCM channel.
Claim 3
Dependent Claim
196 words
A digital signal processor according to claim 1 wherein said ALU includes adder/subtractor means responsive to an add/subtract signal having a first and a second input for selectively generating at an output signals representing the sum or the difference of two numbers from signals applied to said inputs representing said numbers; and overflow detection means responsive to said signals representing said numbers and to a carry-out signal generated by said adder/subtractor means for generating an overflow signal, said processor further including: means responsive to said control signals and to said signals from said external device for storing and generating signals corresponding to coefficient values; means responsive to said overflow signal for generating a plurality of tone control signals; means responsive to a shift control signals connected to said second data bus, for selectively down-shifting a plural-bit quantity represented by signals received via said second data bus and generating at an output signals representative of said down-shifted quantity; and multiplexer means connected to said control, said coefficient storage and generation means, said dual PCM channel, said second data bus, and said tone control generation means, for selectively generating therefrom said add/subtract signal and said shift control signal.
Claim 4
Dependent Claim
58 words
A digital signal processor according to claim 2 further including first and second tone register means each having an output connected to said second data bus, each connected to said external device for receiving and storing signals representative of first and second tone control parameters, respectively, and generating therefrom said tone control signals onto said second data bus.
Claim 5
Dependent Claim
24 words
A digital signal processor according to claim 3 wherein said tone control signals include signals representative of a frequency value, and an amplitude value.
Claim 6
Dependent Claim
47 words
A digital signal processor according to claim 2 further including first mode register means having an output connected to said central control, connected to said external device for receiving and storing signals representative of predetermined ones of said coefficient values and generating therefrom said filter coefficient values.
Claim 7
Dependent Claim
73 words
A digital signal processor according to claim 2 wherein said processor performs a plurality of digital signal processing functions and is responsive to processing function enablement signals further including second mode register means having an output connected to said central control, connected to said external device for receiving and storing signals representative of enablement and disablement of predetermined ones of said digital signal processing functions and generating therefrom said processing function enablement signals.
Claim 8
Dependent Claim
70 words
A digital signal processor according to claim 2 wherein said ALU includes a plurality of circuit elements each performing parallel operations on a predetermined one of said TDM signals, each said circuit element assigned a predetermined time-division slot of at least one of said busses and each said circuit element comprises a plurality of subelements each connected to a predetermined one of the conductors of said at least one bus.
Claim 9
Dependent Claim
20 words
A digital signal processor according to claim 7 wherein predetermined ones of said subelements of a circuit element are replicated.
Claim 10
Dependent Claim
66 words
A digital signal processor according to claim 7 responsive to a plural-phase clock signal wherein predetermined ones of said circuit elements are sources for a predetermined one of said busses during said predetermined time-division slots assigned to said circuit elements, and predetermined ones of said circuit elements are destinations for a predetermined one of said busses during said predetermined time-division slots assigned to said circuit elements.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-01-04 | 1991-07-06 | 1992-01-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-01-04 | 1995-07-06 | 1996-01-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-01-04 | 1999-07-06 | 2000-01-05 | $7700.00 | Window Closed / Lapsed |