US4718036A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Comparator-integrator loop for digitizing a waveform
Assignee: Texas Instruments Tucson Corp
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Filing: 1985-10-28
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Granted: 1988-01-05
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Expires: 2005-10-28
Abstract
Abstract A latching comparator has a signal input connected to the output of a device under test. A strobe input of the comparator has a strobe signal applied thereto, whereby the output of the device under test is repeatedly sampled. The output of the comparator drives an integrator, preferably through a filter. The output of the integrator drives a reference input of the comparator and a computer. The computer is driven via an A/D converter, whereby a digitized representation of the output of the device under test is provided to the computer.
Inventors
- 👤 Joel M. Halbert
- 👤 Myron J. Koen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 10:27
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2832; G01R31/2834; H; H03; H03M; H03M1/00; H03M1/10; H03M1/1071; H03M1/1095
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
115 words
A comparator-integrator loop comprising: a latching comparator with a signal input adapted for connection to the output of a device under test; an operational amplifier with its output coupled to a reference input of said comparator; an integrating capacitor that couples said amplifier output to the inverting input of said amplifier, whereby said amplifier and capacitor form an integrator; filter means disposed between an output of said comparator to the inverting input of said amplifier for rounding off signal spikes; means for clocking a latch enable input of said comparator until the output of said amplifier is in an equilibrium state; and means for establishing a current that flows into the input of said integrator.
Claim 2
Dependent Claim
115 words
A comparator-integrator loop comprising: a latching comparator with a signal input adapted for connection to the output of a device under test; an operational amplifier with its output coupled to a reference input of said comparator; an integrating capacitor that couples said amplifier output to the inverting input of said amplifier, whereby said amplifier and capacitor form an integrator; filter means disposed between an output of said comparator to the inverting input of said amplifier for rounding off signal spikes; means for clocking a latch enable input of said comparator until the output of said amplifier is in an equilibrium state; and means for establishing a current that flows into the input of said integrator.
Claim 3
Dependent Claim
92 words
The comparator-integrator loop of claim 1 wherein said latching comparator includes an analog input stage and an output stage with the latching function occurring in the analog input stage which has a relatively moderate gain and a relatively high bandwidth for substantially eliminating propagation delays and bandwidth limitations in the high gain output stage so as to introduce substantially no error into the accuracy of the measurement, said latch enable input including means for implementing rising-edge triggering of latching to substantially reduce aperture time and further improve the operation of the loop.
Claim 4
Dependent Claim
26 words
The comparator-integrator loop of claim 1 additionally comprising a hold-down resistor operatively coupled between the output of said latching comparator and a source of negative potential.
Claim 5
Dependent Claim
75 words
The comparator-integrator loop of claim 3 wherein said comparator output includes a first inverting output and a second non-inverting output, said filter means having a first section disposed between the inverting output of said latching comparator and the inverting input of said operational amplifier integrator, and a second section disposed between the non-inverting output of said latching comparator and the non-inverting input of said operational amplifier integrator, said first and second sections being substantially identical.
Claim 6
Dependent Claim
36 words
The comparator-integrator loop of claim 4 wherein each section of said filter means includes an RC filter including means for selectively increasing and decreasing the values of a resistance and a capacitance of said RC filter.
Claim 7
Dependent Claim
91 words
The comparator-integrator loop of claim 1 wherein said filter means includes a first filter resistor having one terminal operatively coupled to said latching comparator output; said means for esablishing including a second resistor in series with said first resistor and having one terminal operatively coupled to the opposite terminal of said first filter resistor and its opposite terminal operatively coupled to the inverting input of the operational amplifier integrator; and said filter means further including a filter capacitor operatively coupled between the junction of said first and second resistors and ground.
Claim 8
Dependent Claim
25 words
The comparator-integrator loop of claim 6 including a third resistor coupled between the output of said integrator and a reference input of said latching comparator.
Claim 9
Dependent Claim
70 words
The comparator-integrator loop of claim 7 wherein said filter means includes a fourth resistor having one terminal operatively coupled to the output of the operational amplifier integrator; a fifth resistor operatively coupled between the other terminal of said fourth resistor and a reference input of said latching comparator for forming a feedback loop; and a capacitor operatively coupled between the junction of said fourth and fifth resistors and the ground.
Claim 10
Dependent Claim
81 words
The comparator-integrator loop of claim 6 wherein said feedback loop includes an operational amplifier voltage follower means having at least one input operatively coupled to the output of said operational amplifier for buffering the output of the operational amplifier integrator to prevent current spikes and the like; voltage divider means for establishing a gain factor for the overall comparator-integrator loop; and means for further smoothing the feedback signal and improving the overall accuracy of the integration process of the present system.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-01-04 | 1991-07-06 | 1992-01-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-01-04 | 1995-07-06 | 1996-01-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-01-04 | 1999-07-06 | 2000-01-05 | $7700.00 | Window Closed / Lapsed |