US4717843A
Expired / Lapsed
US
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Phase changing circuit
Assignee: Fujitsu Ltd
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Filing: 1985-07-24
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Granted: 1988-01-05
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Expires: 2005-07-24
Abstract
Abstract A phase changing circuit in a logic circuit includes an ECL circuit which has a plurality of emitter output circuits. One emitter output circuit is used as the normal output. The other emitter output circuits are connected to additional capacitors. The emitter output circuits connected to the additional capacitors are also connected to an emitter output portion of separately provided control ECL circuits. An input control level of the control ECL circuit is changed to change the output level of the control ECL circuit. In accordance with whether the output level of the control ECL circuit is low or high, the additional capacitor affects or does not affect the normal output of the ECL circuit. When the capacitor affects to the normal output of the ECL circuit, the signal propagation from the input to the normal output is delayed.
Inventors
- 👤 Tatsuro Yoshimura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 02:49
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K5/00; H03K5/13; H03K5/131; H03K19/003; H03K19/00323; H03K2005/00013; H03K2005/00078; H03K2005/0015; H03K2005/00163; H03K2005/00176; H03K2005/00182
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
238 words
A phase changing circuit in a logic circuit, said phase changing circuit, connectable to a fixed voltage, receiving input and control signals and outputting an output signal, comprising: an output ECL circuit operatively conencted to receive the input signal, comprising: a buffer circuit, operatively connected to receive the input signal, for generating an internal signal in dependence upon the input signal; a first emitter output circuit, having an input operatively connected to said buffer circuit, for outputting the output signal in dependence upon the internal signal; and a second emitter output circuit having an input operatively connected to said buffer circuit and having an output producing a controlled signal; a first capacitor having a first end operatively connected to the output of said second emitter output circuit and a second end connectable to said fixed voltage; and a first control ECL circuit operatively connected to the first end of said first capacitor and to receive a first control signal, the controlled signal output by said second emitter output circuit being held at a first output level when the first control signal has a first control level and having either the first output level or a second output level in dependence upon the internal signal when the first control signal has a second control level, changes of the output signal in response to changes in the input signal being delayed when the control signal has the second control level.
Claim 2
Dependent Claim
238 words
A phase changing circuit in a logic circuit, said phase changing circuit, connectable to a fixed voltage, receiving input and control signals and outputting an output signal, comprising: an output ECL circuit operatively conencted to receive the input signal, comprising: a buffer circuit, operatively connected to receive the input signal, for generating an internal signal in dependence upon the input signal; a first emitter output circuit, having an input operatively connected to said buffer circuit, for outputting the output signal in dependence upon the internal signal; and a second emitter output circuit having an input operatively connected to said buffer circuit and having an output producing a controlled signal; a first capacitor having a first end operatively connected to the output of said second emitter output circuit and a second end connectable to said fixed voltage; and a first control ECL circuit operatively connected to the first end of said first capacitor and to receive a first control signal, the controlled signal output by said second emitter output circuit being held at a first output level when the first control signal has a first control level and having either the first output level or a second output level in dependence upon the internal signal when the first control signal has a second control level, changes of the output signal in response to changes in the input signal being delayed when the control signal has the second control level.
Claim 3
Dependent Claim
97 words
A phase changing circuit according to claim 1, further comprising: second to n'th capacitors; and second to n'th control ECL circuits operatively connected to said second to n'th capacitors and to receive second to n'th control signals, respectively, and wherein said output ECL circuit further comprises third to n+1'th emitter output circuits, having inputs operatively connected to said first emitter output circuit and outputs respectively connected to said second to n'th capacitors, the input signal being subjected to a signal transmission delay time in said output ECL circuit in dependence upon the first to n'th control signals.
Claim 4
Dependent Claim
45 words
A phase changing circuit according to claim 2, wherein said first to n'th capacitors are formed by wiring patterns, each having a length and a width, said first to n'th capacitors each having a capacitance determined by the length and width of the wiring pattern.
Claim 5
Dependent Claim
40 words
A phase changing circuit according to claim 1, wherein said first capacitor is formed by a wiring pattern having a length and a width, said first capacitor having a capacitance determined by the length and width of the wiring pattern.
Claim 6
Dependent Claim
168 words
An emitter-coupled logic circuit, operatively connected to a power supply, providing a variable delay to an input signal, comprising: an input circuit, operatively connected to receive the input signal, for producing an intermediate signal; a first emitter-coupled logic output circuit having a control terminal operatively connected to receive the intermediate signal and an output terminal providing an output signal changing in dependence upon the input signal with a delay; a second emitter-coupled logic output circuit having a control terminal connected to the control terminal of said first emitter-coupled logic output circuit and having an output terminal; a control gate, operatively connected to receive an input control signal, having an output terminal for outputting an output control signal; and a capacitor, having one end operatively connected to the output terminals of said second emitter-coupled logic output circuit and the control gate and having a second end operatively connected to the power supply, the delay provided by the first emitter-coupled logic output circuit varying in dependence upon the control signal.
Claim 7
Dependent Claim
168 words
An emitter-coupled logic circuit, operatively connected to a power supply, providing a variable delay to an input signal, comprising: an input circuit, operatively connected to receive the input signal, for producing an intermediate signal; a first emitter-coupled logic output circuit having a control terminal operatively connected to receive the intermediate signal and an output terminal providing an output signal changing in dependence upon the input signal with a delay; a second emitter-coupled logic output circuit having a control terminal connected to the control terminal of said first emitter-coupled logic output circuit and having an output terminal; a control gate, operatively connected to receive an input control signal, having an output terminal for outputting an output control signal; and a capacitor, having one end operatively connected to the output terminals of said second emitter-coupled logic output circuit and the control gate and having a second end operatively connected to the power supply, the delay provided by the first emitter-coupled logic output circuit varying in dependence upon the control signal.
Claim 8
Dependent Claim
40 words
A circuit as recited in claim 5, wherein said first and second emitter-coupled logic output circuits comprise first and second NPN transistors, respectively, having bases connected together, collectors connected to the power supply and emitters forming the output terminals thereof.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-01-04 | 1991-07-06 | 1992-01-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-01-04 | 1995-07-06 | 1996-01-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-01-04 | 1999-07-06 | 2000-01-05 | $7700.00 | Window Closed / Lapsed |