US4716587A
Expired / Lapsed
US
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Broadband-signal broadcasting system
Assignee: Telecom Italia SpA
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Filing: 1986-05-08
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Granted: 1987-12-29
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Expires: 2006-05-08
Abstract
Abstract A broadband signal broadcasting system comprising a circuit to encode video and audio signals forming a TV channel to be sent to a switching matrix, which is remotely operated by the subscriber; a circuit to multiplex two or more TV channel to be simultaneously transmitted on the subscriber's line, which can be a coaxial cable, a radio link or an optical fiber; and a circuit to receive the signals transmitted on the line, to separate two or more TV channels and to carry out channel decoding by supplying the subscriber's terminals with the corresponding video and audio signals. The system requires a single encoding and a single decoding of the nB→(n+m)B type on broadband signals, respectively at the output from signal sources and at the input of subscriber's terminals.
Inventors
- 👤 Alfredo Fausone
- 👤 Agostino Moncalvo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 20:17
CPC Classifications
H; H04; H04N; H04N21/00; H04N21/20; H04N21/23; H04N21/238; H04N21/2383; H04N21/236; H04N21/2365; H04N21/2368; H04N21/40; H04N21/43; H04N21/434; H04N21/4341; H04N21/4347; H04N21/438; H04N21/4382; H04N7/00; H04N7/14; H04N7/141; H04N7/148; H04N7/24; H04N7/52; H04N7/54
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
365 words
A broadband broadcasting system having video signals and audio signals originating from various sources, said video signals and said audio signals being processed by said broadcasting system, each of said audio signals having an audio frequency and each of said video signals having a video frequency, said video signals and said audio signals being decoded by subscribers connected in said system by a decoding circuit, said broadcasting system comprising: a first serial-to-parallel converter having a first input and forming at least one output; a first clock coupled to said first serial-to-parallel converter forming a first clock signal with a first clock frequency equal to said video frequency, wherein said first clock signal controls loading of said first serial-to-parallel converter at said first input with said video signal; a first frequency divider coupled to said first clock and said first serial-to-parallel converter, for dividing said first clock signal forming a second clock signal for controlling reading of said serial-to-parallel converter; a first scrambler coupled to said output of first serial-to-parallel converter; a second frequency divider coupled to said first frequency divider and forming a third clock signal; a first converting means comprising at least one serial-to-parallel converter for each output of said first serial-to-parallel converter, coupled to said first frequency divider, said first scrambler and said second frequency divider, wherein said third clock signal controls reading of said converting means; a second scrambler receiving said audio signals; a first memory coupled to said second scrambler, wherein said audio frequency controls loading of said first memory and said third clock signal controls reading of said first memory; an encoding means coupled to said first memory and said converting means for channel encoding said video and said audio signals; a register coupled to said encoding means, said first memory and said third clock signal for storing an output of said encoding means; a multiplexer coupled to said register for combining said output of said register into parallel flow and a frame alignment word; a parallel-to-serial converter coupled to said multiplexer forming a digital TV signal, under serial form with channel encoding; and a switching matrix coupled to said parallel-to-serial converter for selection of television channels by said subscribers.
Claim 2
Dependent Claim
365 words
A broadband broadcasting system having video signals and audio signals originating from various sources, said video signals and said audio signals being processed by said broadcasting system, each of said audio signals having an audio frequency and each of said video signals having a video frequency, said video signals and said audio signals being decoded by subscribers connected in said system by a decoding circuit, said broadcasting system comprising: a first serial-to-parallel converter having a first input and forming at least one output; a first clock coupled to said first serial-to-parallel converter forming a first clock signal with a first clock frequency equal to said video frequency, wherein said first clock signal controls loading of said first serial-to-parallel converter at said first input with said video signal; a first frequency divider coupled to said first clock and said first serial-to-parallel converter, for dividing said first clock signal forming a second clock signal for controlling reading of said serial-to-parallel converter; a first scrambler coupled to said output of first serial-to-parallel converter; a second frequency divider coupled to said first frequency divider and forming a third clock signal; a first converting means comprising at least one serial-to-parallel converter for each output of said first serial-to-parallel converter, coupled to said first frequency divider, said first scrambler and said second frequency divider, wherein said third clock signal controls reading of said converting means; a second scrambler receiving said audio signals; a first memory coupled to said second scrambler, wherein said audio frequency controls loading of said first memory and said third clock signal controls reading of said first memory; an encoding means coupled to said first memory and said converting means for channel encoding said video and said audio signals; a register coupled to said encoding means, said first memory and said third clock signal for storing an output of said encoding means; a multiplexer coupled to said register for combining said output of said register into parallel flow and a frame alignment word; a parallel-to-serial converter coupled to said multiplexer forming a digital TV signal, under serial form with channel encoding; and a switching matrix coupled to said parallel-to-serial converter for selection of television channels by said subscribers.
Claim 3
Dependent Claim
249 words
A broadcasting system as defined in claim 1 for handling at least two digital TV signals in serial form wherein said switching matrix comprises: two rephasing circuits comprised of a delay line operating on a fourth clock signal, said fourth clock signal controlling said parallel-to-serial converter, and said two rephasing circuits being controlled by a phase comparator, said phase comparator comparing phase of said fourth clock signal with phase of said TV signals, each of said two rephasing circuits generating a fifth clock signal; a third frequency divider and fourth frequency divider for dividing said fifth clock signal forming a sixth signal and an seventh clock signal; a first logic means; two frame-aligning circuits coupled to said two rephasing circuits and said switching matrix, each of said two frame-aligning circuits comprised of shift-registers to load and read said TV signals, each of said two frame-aligning circuits being controlled by said first logic means for detecting said frame alignment word; third and fourth serial-to-parallel converters each coupled to one of said two frame-aligning circuits, said third and said fourth serial-to-parallel converters being controlled during loading by said fifth clock signal and controlled during reading by said sixth and seventh clock signals; a second multiplexer coupled to said third and fourth serial-to-parallel converters; a second parallel-to-serial converter coupled to said second multiplexer to convert output of said multiplexer into a single serial flow; and a second logic means coupled to said second multiplexer for transmitting said second multiplexer said frame-alignment word.
Claim 4
Dependent Claim
205 words
A broadcast system as defined in claim 2 wherein said decoding circuit comprises: a fifth serial-to-parallel converter for receiving said serial flow; an aligning circuit coupled to said fifth serial-to-parallel converter for comparing said serial flow with predetermined binary configurations; a fifth frequency divider coupled to said aligning circuit forming an eighth clock signal; a code violation detector coupled to said aligning circuit for detecting code violations; a time selector coupled to said code violation detector for outputting each of a plurality of television channels; a third frame aligning circuit coupled to said time selector; a sixth frequency divider coupled to said fifth frequency divider forming said ninth clock signal; a demultiplexer coupled to said third frame aligning circuit for separating an output of said third aligning circuit controlled by said ninth clock signal; a decoder coupled to said demultiplexer for obtaining an audio serial flow and a parallel video flow; a second converting means comprising at least one serial-to-parallel converter coupled to said demultiplexer for converting said parallel video flow into a serial video flow; a first descrambler coupled to said second converting means for descrambling said serial video flow; and a second descrambler coupled to said demultiplexer for descrambling said serial audio flow.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-12-28 | 1991-06-29 | 1991-12-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-12-28 | 1995-06-29 | 1995-12-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-12-28 | 1999-06-29 | 1999-12-29 | $7700.00 | Window Closed / Lapsed |