Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
280 words
Digital apparatus for a data recovery system wherein the data is read out from a moving magnetic media and is affected by a speed error and by peak shift, said system comprising a unit for measuring the duration of intervals between first and second subsequently read out pulses, a speed correcting unit for converting the measured duration of said intervals into a duration corrected for errors in speed, a peak shift recovery unit for generating signals identifying, depending on the peak shift of a first pulse and the corrected duration of a following interval, a nominal duration of said following interval and the peak shift of the second pulse ending said following interval, said digital apparatus comprising: means for receiving a binary signal representative of the peak shift direction of each subsequent read out pulse; a first counter for counting a preestablished number of subsequent read out pulses; a second counter coupled to said first counter to receive said binary signal to effect the algebric sum of the peak shift direction of said preestablished number of read out pulses and to generate a binary code representative of peak shift difference; and, circuit means having outputs and inputs coupled to receive said binary code from said second counter and a speed error code fed back from said outputs which is representative of a previously measured speed error, said circuit means generating a new, updated speed error code, as a function of said binary code and said previously generated speed error code, said circuit means including means connected to said outputs for applying said updated speed error code to said speed error correcting unit and to said inputs of said circuit means.
Claim 2
Dependent Claim
280 words
Digital apparatus for a data recovery system wherein the data is read out from a moving magnetic media and is affected by a speed error and by peak shift, said system comprising a unit for measuring the duration of intervals between first and second subsequently read out pulses, a speed correcting unit for converting the measured duration of said intervals into a duration corrected for errors in speed, a peak shift recovery unit for generating signals identifying, depending on the peak shift of a first pulse and the corrected duration of a following interval, a nominal duration of said following interval and the peak shift of the second pulse ending said following interval, said digital apparatus comprising: means for receiving a binary signal representative of the peak shift direction of each subsequent read out pulse; a first counter for counting a preestablished number of subsequent read out pulses; a second counter coupled to said first counter to receive said binary signal to effect the algebric sum of the peak shift direction of said preestablished number of read out pulses and to generate a binary code representative of peak shift difference; and, circuit means having outputs and inputs coupled to receive said binary code from said second counter and a speed error code fed back from said outputs which is representative of a previously measured speed error, said circuit means generating a new, updated speed error code, as a function of said binary code and said previously generated speed error code, said circuit means including means connected to said outputs for applying said updated speed error code to said speed error correcting unit and to said inputs of said circuit means.
Claim 3
Dependent Claim
80 words
The digital apparatus of claim 1 wherein said circuit means further comprises: a latching register having inputs and outputs, said inputs being coupled to be periodically loaded with said binary code and said previously measured speed error code, and an addressable memory having a first plurality of locations containing first transcoding codes, first outputs and first address inputs connected to said outputs of said register, said memory being operative to generate a new updated speed error code on first outputs.
Claim 4
Dependent Claim
65 words
The digital apparatus of claim 2 wherein said memory has second address inputs for receiving a code representative of a measured interval duration, second outputs and a second plurality of locations for storing second transcoding codes, said memory being operative to generate on said second outputs, a corrected interval duration code used for speed error correction and for generating a new updated speed error code.