Apparatus for performing desired logical function

Claim 1

An apparatus for performing a desired logical function comprising: an AND array having input lines through which logical variables are inputted, one or more product term lines intersecting the input lines, and first unit circuits positioned at the respective points where the input lines and the product term lines intersect and connected to the input lines and the product term lines, each of the first unit circuits having a first storage means for storing information which determines whether the product term line connected to the first unit circuits is to be sensitized or desensitized and a first means for selectively sensitizing or desensitizing the product term line on the basis of the information stored in the first storage means, the AND array generating desired logical products of the logical variables on the respective product term lines; and an OR array having signal lines connected to the product term lines, respectively, one or more output lines intersecting the signal lines, and second unit circuits positioned at the respective points where the signal lines and the output lines intersect, each of the second unit circuits having a second storage means for storing information which determines whether the output line connected to the each of the second unit circuits is to be sensitized or desensitized and a second means for selectively sensitizing or desensitizing the output line on the basis of the information stored in the first storage means, the OR array generating a desired logical sum of the logical products on the respective output lines.

Claim 2

An apparatus for performing a desired logical function comprising: an AND array having input lines through which logical variables are inputted, one or more product term lines intersecting the input lines, and first unit circuits positioned at the respective points where the input lines and the product term lines intersect and connected to the input lines and the product term lines, each of the first unit circuits having a first storage means for storing information which determines whether the product term line connected to the first unit circuits is to be sensitized or desensitized and a first means for selectively sensitizing or desensitizing the product term line on the basis of the information stored in the first storage means, the AND array generating desired logical products of the logical variables on the respective product term lines; and an OR array having signal lines connected to the product term lines, respectively, one or more output lines intersecting the signal lines, and second unit circuits positioned at the respective points where the signal lines and the output lines intersect, each of the second unit circuits having a second storage means for storing information which determines whether the output line connected to the each of the second unit circuits is to be sensitized or desensitized and a second means for selectively sensitizing or desensitizing the output line on the basis of the information stored in the first storage means, the OR array generating a desired logical sum of the logical products on the respective output lines.

Claim 5

A method of determining logical function of a logic circuit having AND gates and at least one OR gate including signal lines, comprising the steps of: storing information in a storage means, said information determining whether each of the signal lines is to be sensitized or desensitized, connecting each of said AND gates in each of the signal lines by connecting said signal line to one input thereof and to an output thereof, connecting another input of each of the AND gates to a signal indicative of the stored information, connecting an input of said at least one OR gate to the output of each of the AND gates, selectively sensitizing or desensitizing the signal lines on the basis of the stored information, and supplying the output of the OR gate with a signal indicative of the logical function.

Claim 6

A method of determining logical function of a logic circuit having AND gates and at least one OR gate including signal lines, comprising the steps of: storing information in a storage means, said information determining whether each of the signal lines is to be sensitized or desensitized, connecting each of said AND gates in each of the signal lines by connecting said signal line to one input thereof and to an output thereof, connecting another input of each of the AND gates to a signal indicative of the stored information, connecting an input of said at least one OR gate to the output of each of the AND gates, selectively sensitizing or desensitizing the signal lines on the basis of the stored information, and supplying the output of the OR gate with a signal indicative of the logical function.

Claim 9

A method of determining logical function of a logic circuit having OR gates and at least one AND gate including signal lines, comprising the steps of: storing information in the storage means, said information determining whether each of the signal lines is to be sensitized or desensitized, connecting each of said OR gates in each of the signal lines by connecting said signal line to one input thereof and to an output thereof, connecting another input of each of the OR gates to a signal indicative of the stored information, connecting an input of said at least one AND gate to the output of each of the OR gates, selectively sensitizing or desensitizing the signal lines on the basis of the stored information, and supplying the output of the AND gate with a signal indicative of the logical function.

Claim 10

A method of determining logical function of a logic circuit having OR gates and at least one AND gate including signal lines, comprising the steps of: storing information in the storage means, said information determining whether each of the signal lines is to be sensitized or desensitized, connecting each of said OR gates in each of the signal lines by connecting said signal line to one input thereof and to an output thereof, connecting another input of each of the OR gates to a signal indicative of the stored information, connecting an input of said at least one AND gate to the output of each of the OR gates, selectively sensitizing or desensitizing the signal lines on the basis of the stored information, and supplying the output of the AND gate with a signal indicative of the logical function.

Claim 13

An apparatus for performing a desired logical function, having a logic circuit including signal lines, comprising: storage means for storing information which determines whether each of the signal lines is to be sensitized or desensitized, AND gates, each of which is connected in each of the signal lines through one input thereof and an output thereof and having another input thereof connected to receive a signal indicative of the stored information, and at least one OR gate having an input connected to the output of each of the AND gates, whereby the signal lines are selectively sensitized or desensitized and the output of the OR gate is supplied with a signal indicative of the desired logical function on the basis of the information stored in the storage means.

Claim 14

An apparatus for performing a desired logical function, having a logic circuit including signal lines, comprising: storage means for storing information which determines whether each of the signal lines is to be sensitized or desensitized, AND gates, each of which is connected in each of the signal lines through one input thereof and an output thereof and having another input thereof connected to receive a signal indicative of the stored information, and at least one OR gate having an input connected to the output of each of the AND gates, whereby the signal lines are selectively sensitized or desensitized and the output of the OR gate is supplied with a signal indicative of the desired logical function on the basis of the information stored in the storage means.

Claim 17

An apparatus for performing a desired logical function, having a logic circuit including signal lines, comprising: storage means for storing information which determines whether each of the signal lines is to be sensitized or desensitized, OR gates, each of which is connected in each of the signal lines through one input thereof and an output thereof and having another input thereof connected to receive a signal indicative of the stored information, and at least one AND gate having an input connected to the output of each of the OR gates, whereby the signal lines are selectively sensitized or desensitized and the output of the AND gate is supplied with a signal indicative of the desired logical function on the basis of the information stored in the storage means.

Claim 18

An apparatus for performing a desired logical function, having a logic circuit including signal lines, comprising: storage means for storing information which determines whether each of the signal lines is to be sensitized or desensitized, OR gates, each of which is connected in each of the signal lines through one input thereof and an output thereof and having another input thereof connected to receive a signal indicative of the stored information, and at least one AND gate having an input connected to the output of each of the OR gates, whereby the signal lines are selectively sensitized or desensitized and the output of the AND gate is supplied with a signal indicative of the desired logical function on the basis of the information stored in the storage means.