US4703364A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Processor synchronous image scanner controlling method
Assignee: International Business Machines Corp
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Filing: 1986-06-30
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Granted: 1987-10-27
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Expires: 2006-06-30
Abstract
Abstract The invention directly controls the start of application of clock pulses to a shift register of an image sensor unit in synchronism with read signals supplied from a processor unit, to transfer video data of successive scan lines of an image. Transfer time of video data of one scan line from the shift register to the processor unit is compared to a predetermined time period. If the transfer time exceeds the predetermined time period, transfer of video data of the next scan line to the shfit register is allowed after the video data of the one scan line in the shift register has been transferred to the processor unit, whereby electric charges for the next scan line accumulated in the photodiodes are vanished. And, the video data of the next scan line in the shift register is discarded. In addition, the invention is devised to provide a data disposing cycle in the operation mode of the shift register in addition to the data reading cycle, so that, even when interruption from others causes the operation of the processor fetching the video data from the shift register to exceed a predetermined scanning time before completion of the operation, the data disposing cycle is inserted right after completion of the operation to disposed high level data that has been sensed for a long period of time by a photosensor of the sensor unit, and normal level data or image information properly representing an image being scanned is obtained. Furthermore, the invention reduces significantly the processing load of the processor with a simple hardware constitution by adding the operation of a run length counter, etc., so as to enable high speed linear data compression.
Inventors
- 👤 Shigeki Asada
- 👤 Hiroshi Yanagisawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 02:01
CPC Classifications
H; H04; H04N; H04N25/00; H04N25/70; H04N25/71; H04N25/713; G; G06; G06F; G06F3/00; G06F3/002; H04N1/00; H04N1/04; H04N1/17; H04N25/48; H04N5/00; H04N5/04
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
218 words
Method for transferring video data representing an image from a sensor unit to a processor unit in which the sensor unit and the image are moved relative to each other to successively scan said image and the sensor unit includes a photodiode array and a shift register, characterized by steps of: starting to apply clock pulses to the shift register in synchronism with read signal generated by a processor unit to transfer video data of one scan line to the processor unit; determining if a transfer time of the video data of the one scan line from the shift register to the processor unit exceeds a predetermined time period; inhibiting a transfer of video data of next scan line from the photodiode array to the shift register when it is determined that the transfer time of the one scan line exceeds the predetermined time period; allowing the transfer of the video data of the next scan line from the photodiode array to the shift register after the video data of the one scan line has been transferred to the processor unit; discarding the video data of the next scan line from the shift register to reset the shift register; and transferring again the video data of the next scan line from the photodiode array to the shift register.
Claim 2
Dependent Claim
218 words
Method for transferring video data representing an image from a sensor unit to a processor unit in which the sensor unit and the image are moved relative to each other to successively scan said image and the sensor unit includes a photodiode array and a shift register, characterized by steps of: starting to apply clock pulses to the shift register in synchronism with read signal generated by a processor unit to transfer video data of one scan line to the processor unit; determining if a transfer time of the video data of the one scan line from the shift register to the processor unit exceeds a predetermined time period; inhibiting a transfer of video data of next scan line from the photodiode array to the shift register when it is determined that the transfer time of the one scan line exceeds the predetermined time period; allowing the transfer of the video data of the next scan line from the photodiode array to the shift register after the video data of the one scan line has been transferred to the processor unit; discarding the video data of the next scan line from the shift register to reset the shift register; and transferring again the video data of the next scan line from the photodiode array to the shift register.
Claim 3
Dependent Claim
38 words
A method set forth in claim 1, wherein the application of said clock pulses to said shift register is started by making a gate means receiving clock pulses of an oscillator conductive in synchronization with said read signal.
Claim 4
Dependent Claim
25 words
A method set forth in claim 1 or 2, wherein a shift register consisting of a charge transfer device is used as said shift register.
Claim 5
Dependent Claim
23 words
A method set forth in claim 1 or 2 wherein a photodiode connected with a capacitor in parallel is used as said photosensor.
Claim 6
Dependent Claim
137 words
A processor synchronous image scanner controlling method characterized by steps of: starting to apply clock pulses to a shift register in a sensor unit of an image scanner and resetting a run length counter of said image scanner and then starting to apply said clock pulses to said run length counter, in synchronization with a read signal from a processor; detecting a binary change point of binary video data based on output data of said shift register; stopping the application of said clock pulses to said shift register and said run length counter and providing interruption to said processor; supplying a value of said run length counter to said processor to make said processor deal with said value; and causing said processor to output said read signal when said processor becomes available after completion of dealing with.
Claim 7
Dependent Claim
137 words
A processor synchronous image scanner controlling method characterized by steps of: starting to apply clock pulses to a shift register in a sensor unit of an image scanner and resetting a run length counter of said image scanner and then starting to apply said clock pulses to said run length counter, in synchronization with a read signal from a processor; detecting a binary change point of binary video data based on output data of said shift register; stopping the application of said clock pulses to said shift register and said run length counter and providing interruption to said processor; supplying a value of said run length counter to said processor to make said processor deal with said value; and causing said processor to output said read signal when said processor becomes available after completion of dealing with.
Claim 8
Dependent Claim
43 words
A method set forth in claim 5, wherein the application of said clock pulses to said shift register and said run length counter is started by making a gate means receiving clock pulses of an oscillator conductive in synchronization with said read signal.
Claim 9
Dependent Claim
47 words
A method set forth in claim 6, wherein the application of said clock pulses to said shift register and said run length counter is started by setting a latch means with said read signal and making said gate means conductive with output signal from said latch means.
Claim 10
Dependent Claim
63 words
A method set forth in claim 7, wherein stopping the application of said clock pulses to said shift register and said run length counter, and the interruption to said processor are performed by resetting said latch means at the same time that said binary change point is detected, and supplying output signal from said latch means to said gate means and said processor.
References Cited (Backward Citations)
US4150873A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-10-26 | 1991-04-27 | 1991-10-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-10-26 | 1995-04-27 | 1995-10-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-10-26 | 1999-04-27 | 1999-10-27 | $7700.00 | Window Closed / Lapsed |