Signal generator using digital memory

Claim 2

A signal generator with a digital memory for generating a digital signal having a value which varies periodically comprising: a memory having 2 n addresses in each of which a part of data for one period of said digital signal is stored; an address producing circuit supplying an output to said memory and producing an address signal for said memory, a digital control input having a variable value supplied to said address producing circuit and said address signal varying step by step in a predetermined number of intervals corresponding to said digital control input; a detecting circuit receiving an output of said address producing circuit and generating a detection signal when a value of the address produced by said address producing circuit becomes 2 n or more; and an inversion control circuit for inverting the polarity of at least one of the address signals to said memory and the output from said memory in response to said detection signal from said detecting circuit.

Claim 3

A signal generator according to claim 1, wherein a video signal is supplied to said control input which has a variable value and a frequency modulating signal is obtained at the output of said memory.

Claim 4

A signal generator according to claim 1, wherein the data corresponding to a period of one fourth of the period of said digital signal having a periodically variable value is stored in each of said 2 n addresses.

Claim 5

A signal generator for generating various output signals comprising, a memory having 2 n addresses in each of which a part of data for one period is stored, a first polarity inverter supplying an input to said memory, a second polarity inverter receiving the output of said memory, a multiplying circuit receiving a digital control signal and multiplying it by a fixed coefficient, an integrator receiving the output of said multiplying circuit and supplying an input to said first polarity inverter and said integrator receiving a clock pulse, and a flip-flop circuit receiving an output from said integrator and supplying an input to said second polarity inverter.

Claim 6

A signal generator for generating various output signals comprising, a memory having 2 n addresses in each of which a part of data for one period is stored, a first polarity inverter supplying an input to said memory, a second polarity inverter receiving the output of said memory, a multiplying circuit receiving a digital control signal and multiplying it by a fixed coefficient, an integrator receiving the output of said multiplying circuit and supplying an input to said first polarity inverter and said integrator receiving a clock pulse, and a flip-flop circuit receiving an output from said integrator and supplying an input to said second polarity inverter.

Claim 7

A signal generator using a digital memory for generating a frequency modulated digital signal having a value which varies periodically, the signal generator comprising: a memory having 2 n addresses in which data of one period of said digital signal is stored; a circuit for multiplying a digital video signal having a variable value by a predetermined coefficient; and an integrator for integrating the digital video signal multiplied by said coefficient at predetermined clock intervals in order to produce an address signal for said memory, said address signal varying step by step over a predetermined number of clock intervals in dependence on the digital level of said digital video signal and said predetermined coefficient.

Claim 8

A signal generator using a digital memory for generating a frequency modulated digital signal having a value which varies periodically, the signal generator comprising: a memory having 2 n addresses in which data of one period of said digital signal is stored; a circuit for multiplying a digital video signal having a variable value by a predetermined coefficient; and an integrator for integrating the digital video signal multiplied by said coefficient at predetermined clock intervals in order to produce an address signal for said memory, said address signal varying step by step over a predetermined number of clock intervals in dependence on the digital level of said digital video signal and said predetermined coefficient.

Claim 9

A signal generator using a digital memory for generating a frequency modulated digital signal having a value which varies periodically, the signal generator comprising: a memory having 2 n addresses in which data of one period of said digital signal is stored; a circuit for multiplying a digital video signal having a variable value by a predetermined coefficient; an address producing circuit for producing address signals for said memory, the digital video signal multiplied by said predetermined coefficient being supplied to said address producing circuit, and said address signal varying step by step at clock intervals over a predetermined number of clock intervals in dependence on the digital level of said digital video signal and said predetermined coefficient; a detecting circuit for generating a detection signal when the value of the address signal produced by said address producing circuit becomes 2 n-1 or more; and an inversion control circuit for selectively inverting, in response to said detection signal, the polarity of at least one of the read-out output from said memory and the address signals supplied to said memory.

Claim 10

A signal generator using a digital memory for generating a frequency modulated digital signal having a value which varies periodically, the signal generator comprising: a memory having 2 n addresses in which data of one period of said digital signal is stored; a circuit for multiplying a digital video signal having a variable value by a predetermined coefficient; an address producing circuit for producing address signals for said memory, the digital video signal multiplied by said predetermined coefficient being supplied to said address producing circuit, and said address signal varying step by step at clock intervals over a predetermined number of clock intervals in dependence on the digital level of said digital video signal and said predetermined coefficient; a detecting circuit for generating a detection signal when the value of the address signal produced by said address producing circuit becomes 2 n-1 or more; and an inversion control circuit for selectively inverting, in response to said detection signal, the polarity of at least one of the read-out output from said memory and the address signals supplied to said memory.

Claim 11

A signal generator according to claim 6 wherein the data corresponding to a quarter of the period of said digital signal is stored in the 2 n addresses corresponding to said 2 n address signals.