High temperature pressure sensor with low parasitic capacitance

Claim 1

A silicon variable capacitance pressure sensor including: a first lightly doped n (or p)-type silicon wafer having a first cavity with a first p+ (or n+) doped capacitor plate with a highly doped first p+ (or n+) semiconductor path through said first wafer contacting said first capacitance plate; a second lightly doped n (or p)-type silicon wafer having a second p+ doped (or r+) capacitor plate with a highly doped second p+ (or n+) semiconductor path through said second wafer contacting said second capacitor plate; an insulating layer attached to said first and second silicon wafers at a region outside the extent of said first cavity preventing electrically conductive coupling between said first and second wafers, thereby reducing parasitic capacitance between the first and semiconductor paths; said first and second capacitor plates being highly doped semiconductor regions positioned adjacent each other and separated from each other by the depth of said cavity; said insulating layer being formed of silicon dioxide thereby producing a structure suitable for operation at relatively high temperature; and said first and second silicon wafers being adapted for having formed therein an integrated circuit.