US4700467A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for grounding flat devices and integrated circuits
Assignee: Alcatel Lucent Italia SpA
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Filing: 1985-06-07
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Granted: 1987-10-20
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Expires: 2005-06-07
Abstract
Abstract Grounding of source contacts (S) of flat devices and integrated circuits (of the FET type) is carried out according to the following process steps: a GaAs wafer is applied on a support and is covered on its free or rear face with photoresist; the latter is then etched along the border lines of the single FETs; the GaAs layer between contiguous FETs is removed also to make accessible the contacts S; a layer of noble metal is then deposited on the FET rear faces, so that it bridges the contacts S; the single metallized devices are disconnected from the initial support and finally are soldered to a package base.
Inventors
- 👤 Giampiero Donzelli
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 01:57
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/80; H10D30/87; H10D62/00; H10D62/10; H10D62/117; H10D64/00; H10D64/20; H10D64/23; H10D64/251; H10D84/00; H10D84/01; H10D84/02; H10D84/05; H10W; H10W15/00; H10W15/01; H10W72/00; H10W72/01; H10W72/013; H10W72/071; H10W72/073; H10W72/07331; H10W72/07337; H10W72/30; H10W72/351; H10W72/352; H10W72/50; H10W72/551; H10W72/552; H10W72/5522; H10W72/90; H10W72/951; H10W72/952; Y; Y10; Y10S; Y10S148/00; Y10S148/056; Y10S148/126; Y10S148/135
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
237 words
A process for grounding flat devices and integrated circuits, in particular microwave devices, e.g., power FETs, especially of the GaAs type, that consist of a base of Ga arsenide on which three contacts S (source), LD (drain) and G (gate) are provided, characterized in that: (I) a GaAs wafer (W) carrying several flat devices (chips) is fixed on a rigid support (SR); (II) a layer of photoresist (FR) is laid on the free or rear surface of said wafer (W) (i.e., the surface not touching the support); (III) a photomask is made on the photoresist (FR) in order to obtain openings along borders of single devices present on the face of the wafer (W) touching the support; (IV) the GaAs material under said openings made in the photoresist is removed until the single devices are completely separated and the source (S) contacts become accessible; (V) the remaining photoresist still present on the rear of the devices is removed; (VI) metal is deposited over the entire rear surface and side edges of each device and contacts the source (S) of each device on both edges of each device in all the openings formed by the GaAs removal of step IV; (VII) the single devices thus metallized on the rear surface are extracted from the support; and (VIII) the so metallized rear face of the single chips disconnected one from the other is soldered to a grounded package base.
Claim 2
Dependent Claim
237 words
A process for grounding flat devices and integrated circuits, in particular microwave devices, e.g., power FETs, especially of the GaAs type, that consist of a base of Ga arsenide on which three contacts S (source), LD (drain) and G (gate) are provided, characterized in that: (I) a GaAs wafer (W) carrying several flat devices (chips) is fixed on a rigid support (SR); (II) a layer of photoresist (FR) is laid on the free or rear surface of said wafer (W) (i.e., the surface not touching the support); (III) a photomask is made on the photoresist (FR) in order to obtain openings along borders of single devices present on the face of the wafer (W) touching the support; (IV) the GaAs material under said openings made in the photoresist is removed until the single devices are completely separated and the source (S) contacts become accessible; (V) the remaining photoresist still present on the rear of the devices is removed; (VI) metal is deposited over the entire rear surface and side edges of each device and contacts the source (S) of each device on both edges of each device in all the openings formed by the GaAs removal of step IV; (VII) the single devices thus metallized on the rear surface are extracted from the support; and (VIII) the so metallized rear face of the single chips disconnected one from the other is soldered to a grounded package base.
Claim 3
Dependent Claim
154 words
A process according to claim 1, characterized in that: in step (I) the wafer is fixed on the support by means of glue; in step (IV) the GaAs is removed until the chips are fully separated one from the other, and the S contacts become accessible by means of selective chemical etching with e.g. a water solution containing H 3 PO 4 and H 2 O 2 (which does not etch the metallization of the source contact); the remaining photoresist is removed (V by means of organic solvents e.g. acetone; metallization (VI) of the rear face of the single devices is performed with electrolitic or preferably electroless gold; in step (VII) the single devices are extracted from the support by means of organic solvents like trichloroethylene; and the metallized rear face of the single chips is mounted (VIII) on the package base by means of an AuSn soldering alloy or of silver loaded resins.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-10-19 | 1991-04-20 | 1991-10-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-10-19 | 1995-04-20 | 1995-10-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-10-19 | 1999-04-20 | 1999-10-20 | $7700.00 | Window Closed / Lapsed |