Adder circuit for encoded PCM samples

Claim 1

An adder circuit for use in a digital sign processing system which includes a source of pulse code modulation (PCM) samples, each sample having sign, exponent and mantissa fields, said adder circuit comprising: an exponent subtractor circuit, connected to said source of PCM samples, and operative to select one of said exponents from a pair of PCM samples, to provide signals representative of the difference in value of said exponents, and to provide signals identifying the selected exponent, a mantissa shifter circuit, connected to said source of PCM samples and to said exponent subtractor circuit, and operative in response to said signals identifying the selected exponent to shift the mantissa associated with the other exponent by a number of bit positions equal to said difference in exponent values, whereby the mantissa of one sample is adjusted to reflect an exponent of the same value as the selected exponent; a mantissa adder circuit comprising, a sign bit exclusive-OR gate connected to said source of PCM samples and operative in response to sign bits of the same value, from each of a sample pair, to provide a summation signal representative of the sum of said shifted mantissa and the mantissa associated with the selected exponent; and further operative in response to sign bits, of different values from each of a sample pair to provide a difference signal representative of the difference between said shifted mantissa and the mantissa associated with the selected exponent, a first plurality of exclusive-OR gates connected to said mantissa shifter circuit and to said sign bit exclusive-OR gate; a binary adder connected to said plurality of exclusive-OR gates and to said mantissa shifter circuit; said plurality of exclusive-OR gates being operative in response to said sign control signal of a first or second characteristic to gate or invert mantissa bits associated with one of said pair of PCM samples to said mantissa adder circuit; said binary adder being operative to add said gated or inverted bits from said plurality of exclusive-OR gates to mantissa bits associated with the other of said pair of PCM samples, whereby the mantissas of said samples are added to or subtracted from each other depending on the value of their associated sign bits, after being adjusted to reflect a common exponent; said binary added further operative to provide addition signals representative of the results of said add operation, and carry signals of first and second characteristics, indicating the presence and absence, respectively, of a carry condition during said add operations; a sign bit generator connected to said source of PCM samples and said mantissa adder circuit comprising, first and second AND gates, each having a first input connected to said source of PCM samples, and a second input connected to said binary adder; said first AND gate being operative in response to said sign bit of a first value from one of said PCM samples and said carry signal of a first characteristic to provide a first gate signal; said second AND gate being operative in response to said sign bit of a second value from the other of said PCM samples and said carry signal of a second characteristic to provide a second gate signal; and an OR gate connected to said first and second AND gates, and operative in response to said first or second gate signal to provide an output sign bit of a value representative of the results of said add operation.