US4697248A
Expired / Lapsed
US
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Arithmetic circuit for obtaining the vector product of two vectors
Assignee: Sony Corp
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Filing: 1984-12-21
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Granted: 1987-09-29
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Expires: 2004-12-21
Abstract
Abstract In an arithmetic circuit, a first input of m bits representing the vector expression of a first set of elements of a finite field GF(2m) is converted into the components of a matrix, and each component of the matrix is multiplied by second input of m bits representing the vector expression of a second set of elements of the finite field. A vector product of the first and second inputs is thereby obtained.
Inventors
- 👤 Norihisa Shirota
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 15:22
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/60; G06F7/72; G06F7/724; H; H03; H03M; H03M13/00; H03M13/03; H03M13/033; H03M13/05; H03M13/13; H03M13/15; H03M13/151
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
96 words
An arithmetic circuit comprising: means for generating as a first input a first set of m bits representing a first vector of a finite field GF(2m) and for generating as a second input a second set of m bits representing a second vector of said finite field; means for converting said first set of m bits into components of a matrix corresponding to said first vector; and means for multiplying each of said components by said second set of m bits, thereby to obtain as an output a vector product of said first and second inputs.
Claim 2
Dependent Claim
96 words
An arithmetic circuit comprising: means for generating as a first input a first set of m bits representing a first vector of a finite field GF(2m) and for generating as a second input a second set of m bits representing a second vector of said finite field; means for converting said first set of m bits into components of a matrix corresponding to said first vector; and means for multiplying each of said components by said second set of m bits, thereby to obtain as an output a vector product of said first and second inputs.
Claim 3
Dependent Claim
33 words
An arithmetic circuit according to claim 1, in which said converting means comprises a shift register which has a plurality of stages and a feedback loop corresponding to coefficients of a generator polynomial.
Claim 4
Dependent Claim
70 words
An arithmetic circuit according to claim 2, in which said converting means further comprises a clock pulse generator, from which a clock pulse is supplied to said shift register, so that a value stored in said shift register is sequentially shifted in response to said clock signal, and means for generating a plurality of outputs from each stage of said shift register at every clock signal to obtain said components.
Claim 5
Dependent Claim
96 words
An arithmetic circuit according to claim 3, in which said shift register comprises a plurality of sets of exclusive-OR gates which are connected one after another in such a manner that the exclusive-OR gates of one set produce outputs ranging from a most significant bit to a least significant bit that are respectively applied to one bit higher inputs of the exclusive-OR gates of a following set, and that the most significant bit output of the exclusive-OR gates of said one set becomes a least significant bit input of the exclusive-OR gates of said following set.
Claim 6
Dependent Claim
35 words
An arithmetic circuit according to claim 4, in which said multiplying means comprises a plurality of AND gates to which each of said components and each bit of said second set of bits are supplied.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-09-28 | 1991-03-30 | 1991-09-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-09-28 | 1995-03-30 | 1995-09-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-09-28 | 1999-03-30 | 1999-09-29 | $7700.00 | Window Closed / Lapsed |