Current sharing circuit

Claim 2

A controller circuit, comprising: a source of potential; a load; a first power transistor having a collector-emitter circuit and including a collector, an emitter and a base; a second power transistor having a collector, an emitter, and a base, said source, said load and said collector-emitter circuit all being connected in series, said second transistor collector and emitter being connected to said first transistor collector and emitter respectively, and synchronous means connected to said transistor bases for gating said first transistor on while maintaining said second transistor at cut-off and vice versa.

Claim 3

The invention as defined in claim 1, wherein: a voltage regulating device is connected between said first transistor collector and emitter.

Claim 4

The invention as defined in claim 1, wherein: said source, said load and said collector-emitter circuit are all directly connected, said second transistor collector and emitter being directly connected to said first transistor collector and emitter, respectively.

Claim 5

The invention as defined in claim 3, wherein a voltage regulating device is connected between said first transistor collector and emitter.

Claim 6

The invention as defined in claim 4, wherein said load is an inductive load.

Claim 7

A controller circuit, comprising: a source of potential; a load; first, second . . . Nth power circuits having their outputs connected in parallel, said power circuit outputs being connected in series with said source and said load; and synchronous means to apply a gating pulse to each of said power circuits in digital succession, all of said gating pulses occurring over mutually exclusive periods of time.

Claim 8

A controller circuit, comprising: a source of potential; a load; first, second . . . Nth power circuits having their outputs connected in parallel, said power circuit outputs being connected in series with said source and said load; and synchronous means to apply a gating pulse to each of said power circuits in digital succession, all of said gating pulses occurring over mutually exclusive periods of time.

Claim 9

A controller circuit, comprising: an oscillator; a flip flop connected from said oscillator to produce first and second complementary bilevel signals at a first pulse repetition frequency (PRF); first means for providing first pulses at a second PRF which is an order of magnitude higher than said first PRF; first and second NAND gates connected from said flip flop to receive said first and second signals, respectively, said NAND gates also each being supplied with a second input of said first pulses; a source of potential; a load; a first power transistor having a collector-emitter circuit and including a collector, an emitter and a base: a second power transistor having a collector, an emitter and a base; said source, said load and said collector-emitter circuit all being connected in series, said second transistor collector and emitter being connected to said first transistor collector and emitter, respectively; second means for gating said first transistor on when the output of said first NAND gate is low; and third means for gating said second transistor on when the output of said second NAND gate is low.

Claim 10

A controller circuit, comprising: an oscillator; a flip flop connected from said oscillator to produce first and second complementary bilevel signals at a first pulse repetition frequency (PRF); first means for providing first pulses at a second PRF which is an order of magnitude higher than said first PRF; first and second NAND gates connected from said flip flop to receive said first and second signals, respectively, said NAND gates also each being supplied with a second input of said first pulses; a source of potential; a load; a first power transistor having a collector-emitter circuit and including a collector, an emitter and a base: a second power transistor having a collector, an emitter and a base; said source, said load and said collector-emitter circuit all being connected in series, said second transistor collector and emitter being connected to said first transistor collector and emitter, respectively; second means for gating said first transistor on when the output of said first NAND gate is low; and third means for gating said second transistor on when the output of said second NAND gate is low.

Claim 11

The invention as defined in claim 7, wherein said first means includes a manually adjustable pulse width modulator.

Claim 12

The invention as defined in claim 8, wherein said load is a wheelchair motor.

Claim 13

The invention as defined in claim 9, wherein said source, said load and said collector-emitter circuit are all directly connected; said second transistor, collector and emitter being directly connected to said first transistor, collector and emitter, respectively.

Claim 14

The invention as defined in claim 10 wherein: a voltage regulating device is connected between the collector and emitter of said first transistor.