Arrangement for deciphering and decoding television pictures encoded in accordance with the MAC standard and scrambled at transmission by submitting the video signals to cyclic permutations

Claim 1

A digital circuit for decoding television picture signals comprising separate components of the MAC type which are scrambled with cyclic permutations, said scrambled signal being descrambled from addresses X 1 of points of cut produced by a pseudo-random address generator comprising: two two-way circuits receiving from an analog to digital converter said scrambled signal in serial digital form for processing the luminance component and four two-way circuits for processing the chrominance component, each comprising: a circuit for converting the serial digital signal information in two rearranged bytes, whereby a writing speed for memories which are to receive said serial digital signal is accommodated such that the access rate of the memory columns are equal to the sampling frequency F s of the analog to digital converter divided by the length of two digital words 2L, said bytes comprising even and odd bytes suitable for writing in separate low and high portions of a respective memory; two sets of memories which are alternately read and written with said serial digital signal data, each memory having n1 cells equal to the length of the useful signal on which said cyclic permutations are effected, comprising: first and second luminance memories Y 1 and Y 2 receiving during the luminance interval the digital luminance signals from said converter circuit, and four chrominance memories C 1 , C 2 , C 3 and C 4 for receiving during the chrominance interval digital chrominance signals from said converter circuit, each of said memories having a high portion and a low portion and an associated read amplifier, a read/write circuit for writing and reading data to and from said memories, including a permutating circuit connecting a high portion to a low portion address circuit, whereby alternately received even and odd bytes are written into high and low portions of each memory; and a parallel to series conversion register for serially rearranging data read from a memory; and, a circuit for decoding the address of the points of cut of the MAC type signal from information supplied by a pseudo-random sequence generator which supplies column addresses of the memories Y 1 , Y 2 , C 1 , C 2 , C 3 and C 4 and which directs during a write phase of said memories data bytes to said memories.