Analog-digital converter

Claim 1

An apparatus for the analog to digital conversion of signal, comprising: (a) a plurality of stages for performing the conversion algorithm V out =2|V in |-V ref , wherein V in is the voltage at the input of a particular stage, V out is the voltage at the output of that stage and becomes the V in to the following stage, and V ref is a chosen reference voltage, each stage comprising (i) a comparator means for comparing V in with a second reference voltage for obtaining a bit of information, (ii) a first input sampling capacitor, (iii) a second feedback capacitor, wherein the capacitance of said first input sampling capacitor is twice that of said feedback capacitor, (iv) a third switch capacitor, (v) a switching network for permitting the charging and discharging of said input sampling capacitor, said feedback capacitor, and said switch capacitor according to predetermined clocking, (vi) an operational amplifier having said input sampling capacitor bridging its inverting and noninverting inputs via said switching network, and said feedback capacitor feeding back from the operational amplifier output to its inverting input, wherein said switching network is arranged to switch the connections of the plates of said input sampling capacitor to said operational amplifier inputs as a function of said clocking and said obtained bit of information from said comparator of said stage to effectuate rectification of V in , and wherein said switching network is arranged to switch the connection of said switch capacitor as a function of said clocking from being connected to the output of said operational amplifier to being between the source of said chosen voltage reference and said inverting input of said operational amplifier, and (b) a plurality of shift registers, each shift register corresponding to a particular stage and having a storage capacity of m bits of information, where m is chosen from .0. to n-1 and is the number of said particular stage with n-1 representing the most significant bit and .0. representing the least significant bit, wherein n is the number of bits output by said analog to digital converter, wherein the output of said shift registers provides an output word in Gray code.

Claim 2

An apparatus for the analog to digital conversion of signal, comprising: (a) a plurality of stages for performing the conversion algorithm V out =2|V in |-V ref , wherein V in is the voltage at the input of a particular stage, V out is the voltage at the output of that stage and becomes the V in to the following stage, and V ref is a chosen reference voltage, each stage comprising (i) a comparator means for comparing V in with a second reference voltage for obtaining a bit of information, (ii) a first input sampling capacitor, (iii) a second feedback capacitor, wherein the capacitance of said first input sampling capacitor is twice that of said feedback capacitor, (iv) a third switch capacitor, (v) a switching network for permitting the charging and discharging of said input sampling capacitor, said feedback capacitor, and said switch capacitor according to predetermined clocking, (vi) an operational amplifier having said input sampling capacitor bridging its inverting and noninverting inputs via said switching network, and said feedback capacitor feeding back from the operational amplifier output to its inverting input, wherein said switching network is arranged to switch the connections of the plates of said input sampling capacitor to said operational amplifier inputs as a function of said clocking and said obtained bit of information from said comparator of said stage to effectuate rectification of V in , and wherein said switching network is arranged to switch the connection of said switch capacitor as a function of said clocking from being connected to the output of said operational amplifier to being between the source of said chosen voltage reference and said inverting input of said operational amplifier, and (b) a plurality of shift registers, each shift register corresponding to a particular stage and having a storage capacity of m bits of information, where m is chosen from .0. to n-1 and is the number of said particular stage with n-1 representing the most significant bit and .0. representing the least significant bit, wherein n is the number of bits output by said analog to digital converter, wherein the output of said shift registers provides an output word in Gray code.

Claim 7

An apparatus for the analog to digital conversion of signal according to the conversion algorithm V out =2|V in |-V ref , wherein V in is the voltage at the input of the apparatus, V out is the voltage at the output of the apparatus, and V ref is a chosen reference voltage, the apparatus comprising: (a) a comparator means for comparing V in with a second reference voltage for obtaining a bit of information, (b) a first input sampling capacitor, (c) a second feedback capacitor, wherein the capacitance of said first input sampling capacitor is twice that of said feedback capacitor, (d) a third switch capacitor, (e) a switching network for permitting the charging and discharging of said input sampling capacitor, said feedback capacitor, and said switch capacitor according to predetermined clocking, and (f) an operational amplifier having said input sampling capacitor bridging its inverting and noninverting inputs via said switching network, and said feedback capacitor feeding back from the operational amplifier output to its inverting input, wherein said switching network is arranged to switch the connections of the plates of said input sampling capacitor to said operational amplifier inputs as a function of said clocking and said obtained bit of information from said comparator to effectuate rectification of V in , and wherein said switching network is arranged to switch the connection of said switch capacitor as a function of said clocking from being connected to the output of said operational amplifier to being between the source of said chosen voltage reference and said inverting input of said operational amplifier, and the voltage at the output of said operational amplifier is V out and may be compared by a comparator means to said second reference voltage to provide a second bit of information.

Claim 8

An apparatus for the analog to digital conversion of signal according to the conversion algorithm V out =2|V in |-V ref , wherein V in is the voltage at the input of the apparatus, V out is the voltage at the output of the apparatus, and V ref is a chosen reference voltage, the apparatus comprising: (a) a comparator means for comparing V in with a second reference voltage for obtaining a bit of information, (b) a first input sampling capacitor, (c) a second feedback capacitor, wherein the capacitance of said first input sampling capacitor is twice that of said feedback capacitor, (d) a third switch capacitor, (e) a switching network for permitting the charging and discharging of said input sampling capacitor, said feedback capacitor, and said switch capacitor according to predetermined clocking, and (f) an operational amplifier having said input sampling capacitor bridging its inverting and noninverting inputs via said switching network, and said feedback capacitor feeding back from the operational amplifier output to its inverting input, wherein said switching network is arranged to switch the connections of the plates of said input sampling capacitor to said operational amplifier inputs as a function of said clocking and said obtained bit of information from said comparator to effectuate rectification of V in , and wherein said switching network is arranged to switch the connection of said switch capacitor as a function of said clocking from being connected to the output of said operational amplifier to being between the source of said chosen voltage reference and said inverting input of said operational amplifier, and the voltage at the output of said operational amplifier is V out and may be compared by a comparator means to said second reference voltage to provide a second bit of information.