MOS type semiconductor device

Claim 2

A MOS type semiconductor device of three semiconductor layer structure comprising: a first semiconductor layer of a first conductivity type comprising a semiconductor substrate; a second semiconductor layer of a second conductivity type comprising an impurity diffusion layer of a second conductivity type formed in said first semiconductor layer, said impurity diffusion layer forming an element of a gate-protecting circuit and comprising an input section diffusion layer of said second conductivity type of said gate-protecting circuit, said input section diffusion layer being connected to an external input terminal to which an input voltage is applied; and a third semiconductor layer of said second conductivity type comprising a plurality of impurity diffusion layers of said second conductivity type formed in said first semiconductor layer, said plural impurity diffusion layers forming elements of a circuit other than said gate-protecting circuit, said plural impurity diffusion layers of said other circuit being separated from each other by at least a first predetermined minimum distance, said plural impurity diffusion layers of said third semiconductor layer being separated from said input section diffusion layer of said second semiconductor layer by a second distance, the second distance being determined to have a value of ten times or more than said first predetermined minimum distance for protecting said gate-protecting circuit from destruction in response to a surge voltage applied to said gate-protecting circuit through said external input terminal.

Claim 3

A MOS type semiconductor device according to claim 1, wherein said other circuit includes an internal circuit whose input section is protected by said gate protecting circuit.

Claim 4

A MOS type semiconductor device according to claim 2, wherein said second distance between said input section layer and the diffusion layers in said other circuit is 30 μm or more.

Claim 5

A MOS type semiconductor device according to claim 2, wherein said second distance between said input section layer and the diffusion layers in said other circuit is 150 μm or less.

Claim 6

A MOS type semiconductor device according to claim 2, wherein said impurity diffusion layer in said gate protecting circuit is composed of said input section layer and a resistive element layer, and a third distance between said resistive element layer and the diffusion layers in said other circuit is 150 μm or less.

Claim 7

A MOS type semiconductor device according to claim 1, wherein said second distance between said input section layer and the diffusion layers in said other circuit is 30 μm or more.

Claim 8

A MOS type semiconductor device according to claim 1, wherein said second distance between said input section layer and the diffusion layers in said other circuit is 150 μm or less.

Claim 9

A MOS type semiconductor device according to claim 1, wherein said impurity diffusion layer in said gate protecting circuit is composed of said input section layer and a resistive element layer, and a third distance between said resistive element layer and the diffusion layers in said other circuit is 20 μm or more.

Claim 10

A MOS type semiconductor device according to claim 2, wherein said impurity diffusion layer in said gate protecting circuit is composed of said input section layer and a resistive element layer, and a third distance between said resistive element layer and the diffusion layers in said other circuit is 20 μm or more.

Claim 11

A MOS type semiconductor device according to claim 1, wherein said impurity diffusion layer in said gate protecting circuit is composed of said input section layer and a resistive element layer, and a third distance between said resistive element layer and the diffusion layers in said other circuit is 150 μm or less.

Claim 12

A MOS type semiconductor device according to claim 1, wherein said plural impurity diffusion layers are applied with a fixed potential when the MOS type semiconductor device operates.

Claim 13

A MOS type semicondcutor device of three semiconductor layer structure comprising: a first semiconductor layer of a first conductivity type comprising a semiconductor substrate; a second semiconductor layer of a second conductivity type comprising a first plurality of impurity diffusion layers of a second conductivity type, formed in said first semiconductor layer, said plural impurity diffusion layers forming elemnts of gate-protecting circuits and comprising input section diffusion layers of said second conductivity type of said gate-protecting circuits, said input section diffusion layers being connected to external input terminals to which input voltages are applied; and a third semiconductor layer of said second conductivity type comprising a plurality of second impurity diffusion layers of second conductivity type formed in said first semiconductor layer, said second plural impurity diffusion layers forming elements of a circuit other than said gate-protecting circuits, said second plural impurity diffusion layers of said other circuit being separated from each other by at least a first predetermined minimum distance, said second plural diffusion layers of said third semiconductor layer being separated from said input section diffusion layers of said second semiconductor layer by second distances, the second distances being determined to have a valve ten times or more than said first predetermined minimum distance for protecting said gate-protecting circuits from destruction in response to surge voltages applied to said gate-protecting circuits through said external input terminals.

Claim 14

A MOS type semicondcutor device of three semiconductor layer structure comprising: a first semiconductor layer of a first conductivity type comprising a semiconductor substrate; a second semiconductor layer of a second conductivity type comprising a first plurality of impurity diffusion layers of a second conductivity type, formed in said first semiconductor layer, said plural impurity diffusion layers forming elemnts of gate-protecting circuits and comprising input section diffusion layers of said second conductivity type of said gate-protecting circuits, said input section diffusion layers being connected to external input terminals to which input voltages are applied; and a third semiconductor layer of said second conductivity type comprising a plurality of second impurity diffusion layers of second conductivity type formed in said first semiconductor layer, said second plural impurity diffusion layers forming elements of a circuit other than said gate-protecting circuits, said second plural impurity diffusion layers of said other circuit being separated from each other by at least a first predetermined minimum distance, said second plural diffusion layers of said third semiconductor layer being separated from said input section diffusion layers of said second semiconductor layer by second distances, the second distances being determined to have a valve ten times or more than said first predetermined minimum distance for protecting said gate-protecting circuits from destruction in response to surge voltages applied to said gate-protecting circuits through said external input terminals.

Claim 15

A MOS type semiconductor device according to claim 12, wherein said second plural impurity diffusion layers are applied with a fixed potential when the MOS type semiconductor device operates.

Claim 16

A MOS type semiconductor device according to claim 12, wherein said second distances are 150 μm or less.

Claim 17

A MOS type semiconductor device according to claim 12, wherein said second distances are 30 μm or more.

Claim 18

A MOS type semiconductor device according to claim 12, wherein distances between said diffusion layers of adjacent two of said gate protecting circuits are substantially equal to said second distances.

Claim 19

A MOS type semiconductor device according to claim 16, wherein said distances between said diffusion layers of two adjacent gate protecting circuits are 30 μm or more.

Claim 20

A MOS type semiconductor device according to claim 16, wherein said distances between said diffusion layers of two adjacent gate protecting circuits are 30 μm or more.