US4686759A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing a semiconductor device
Assignee: US Philips Corp
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Filing: 1984-09-12
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Granted: 1987-08-18
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Expires: 2004-09-12
Abstract
Abstract Method of manufacturing a semiconductor device and semiconductor device manufactured by the use of such a method. A method of contacting narrow regions, such as narrow polysilicon gates of a CCD, having widths of, for example, 4 μm. Upper layers, which are required for the CCD electrodes, are used as etching masks for contacts to the lower electrode layers. Two upper layers define two contact openings of 4 μm which are displaced both with respect to each other and with respect to the region to be contacted. Therefore it is possible to define a contact opening which is smaller than 4 μm and which is aligned accurately above the gate to be contacted.
Inventors
- 👤 Jan A. Pals
- 👤 Arend J. Klinkhamer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 17:45
CPC Classifications
H; H10; H10D; H10D44/00; H10D44/01; H10D44/041; H10D44/40; H10D44/45
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
172 words
A method of manufacturing an integrated circuit, said method comprising the steps of: providing a semiconductor body having a surface and a contact region on the surface, said contact region having first and second opposite edges; and then forming a first dielectric layer on the surface of the body, said first dielectric layer covering the contact region on its edges; forming a first electrode layer on the first dielectric layer, said first electrode layer covering the first edge of the contact region; forming a second dielectric layer on the first electrode layer; forming a second dielectric layer on the second dielectric layer and on exposed portions of the first dielectric layer, said second electrode layer covering the second edge of the contact region, said first and second electrode layers forming a mask with an opening over the contact region; and removing the dielectric over the contact region through the mask opening by selectively etching the dielectric with respect to the electrode layers to form a contact window in the first dielectric layer.
Claim 2
Independent Claim
172 words
A method of manufacturing an integrated circuit, said method comprising the steps of: providing a semiconductor body having a surface and a contact region on the surface, said contact region having first and second opposite edges; and then forming a first dielectric layer on the surface of the body, said first dielectric layer covering the contact region on its edges; forming a first electrode layer on the first dielectric layer, said first electrode layer covering the first edge of the contact region; forming a second dielectric layer on the first electrode layer; forming a second dielectric layer on the second dielectric layer and on exposed portions of the first dielectric layer, said second electrode layer covering the second edge of the contact region, said first and second electrode layers forming a mask with an opening over the contact region; and removing the dielectric over the contact region through the mask opening by selectively etching the dielectric with respect to the electrode layers to form a contact window in the first dielectric layer.
Claim 3
Dependent Claim
29 words
A method as claimed in claim 1, characterized in that each electrode layer comprises at least two separate portions, at least one of which functions solely as a mask.
Claim 4
Dependent Claim
40 words
A method as claimed in claim 2, characterized in that the body comprises: a semiconductor body coated with a thin oxide layer; and a gate electrode on the oxide layer, a portion of said gate electrode froming the contact region.
Claim 5
Dependent Claim
137 words
A method as claimed in claim 1, characterized in that: the body has first and second contact regions, each contact region having first and second opposite edges, both first edges being on a corresponding side of both contact regions, both second edges being on an opposite corresponding side of both contact regions; the first electrode layer covers the first edge of the first contact region and the second edge of the second contact region; the second electrode layer covers the second edge of the first contact region and the first edge of the second contact region, said first and second electrode layers forming a mask with openings over the first and second contact regions; and the dielectric layer is removed over both contact regions through the mask openings to form contact windows in the first dielectric layer.
Claim 6
Dependent Claim
59 words
A method as claimed in claim 4, characterized in that: the first electrode layer does not cover the second edge of the first contact region or the first edge of the second contact region; and the second electrode layer does not cover the first edge of the first contact region or the second edge of the second contact region.
Claim 7
Dependent Claim
16 words
A method as claimed in claim 5, characterized in that the electrode layers comprise polycrystalline silicon.
Claim 8
Dependent Claim
29 words
A method as claimed in claim 6, characterized in that the first and second electrodes are arranged in rows to form the gate electrodes of a charge coupled device.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-08-17 | 1991-02-16 | 1991-08-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-08-17 | 1995-02-16 | 1995-08-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-08-17 | 1999-02-16 | 1999-08-18 | $7700.00 | Window Closed / Lapsed |