US4683447A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Varactor tuning circuit for dielectric resonator stabilized oscillator
Assignee: Eaton Corp
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Filing: 1986-12-01
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Granted: 1987-07-28
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Expires: 2006-12-01
Abstract
Abstract Tuning varactor circuitry is disclosed for a dielectric resonator stabilized oscillator (2). A varactor diode (22) is electrically connected in a loop (24) with an RF bypass capacitor (26), and the voltage across the diode is varied. In a first embodiment, first and second dielectric substrates (36, 38) face each other along the plane of the loop (24), with the loop (24) therebetween. In another embodiment, the loop (24) is around a peripheral side wall (52) of the dielectric resonator substrate (46). In another embodiment, the loop (24) is formed on the same surface (54) of a microstrip circuit substrate (56) with a transmission line (10).
Inventors
- 👤 Ashok K. Talwar
- 👤 William E. Poole, Jr.
- 👤 Richard B. Steinkolk
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 22:38
CPC Classifications
H; H03; H03B; H03B5/00; H03B5/18; H03B5/1864; H03B5/187; H03B2200/00; H03B2200/003; H03B2200/004; H03B2201/00; H03B2201/02; H03B2201/0208; H03B5/1841; H03B5/1847
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
59 words
A tuning varactor circuit for a dielectric resonator stabilized oscillator, comprising a varactor diode electrically connected in an electrically conductive loop with an RF bypass capacitor and having a pair of terminals for applying bias voltage across said diode, and first and second dielectric resonator substrates facing each other along the plane of said loop, with said loop therebetween.
Claim 2
Dependent Claim
59 words
A tuning varactor circuit for a dielectric resonator stabilized oscillator, comprising a varactor diode electrically connected in an electrically conductive loop with an RF bypass capacitor and having a pair of terminals for applying bias voltage across said diode, and first and second dielectric resonator substrates facing each other along the plane of said loop, with said loop therebetween.
Claim 3
Dependent Claim
32 words
The invention according to claim 1 wherein at least one of said substrates has a channel formed therein receiving said loop and said terminals, such that said substrates flushly abut each other.
Claim 4
Dependent Claim
64 words
A tuning varactor circuit for a dielectric resonator stabilized oscillator, comprising a dielectric resonator substrate having top and bottom surfaces and having a peripheral side wall therearound, a varactor diode electrically connected in an electrically conductive loop with an RF bypass capacitor and having a pair of terminals for applying bias voltage across said diode, said loop being disposed around said peripheral side wall.
Claim 5
Dependent Claim
64 words
A tuning varactor circuit for a dielectric resonator stabilized oscillator, comprising a dielectric resonator substrate having top and bottom surfaces and having a peripheral side wall therearound, a varactor diode electrically connected in an electrically conductive loop with an RF bypass capacitor and having a pair of terminals for applying bias voltage across said diode, said loop being disposed around said peripheral side wall.
Claim 6
Dependent Claim
65 words
A tuning varactor circuit for a dielectric resonator stabilizer oscillator, comprising a microstrip circuit substrate having a top planar surface, a transmission line formed on said top surface, a varactor diode and an RF bypass capacitor electrically connected in an electrically conductive loop formed on said top surface adjacent said transmission line and having a pair of terminals for applying bias voltage across said diode.
Claim 7
Dependent Claim
65 words
A tuning varactor circuit for a dielectric resonator stabilizer oscillator, comprising a microstrip circuit substrate having a top planar surface, a transmission line formed on said top surface, a varactor diode and an RF bypass capacitor electrically connected in an electrically conductive loop formed on said top surface adjacent said transmission line and having a pair of terminals for applying bias voltage across said diode.
References Cited (Backward Citations)
US4121182A
Cited
GB2141880A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-07-27 | 1991-01-26 | 1991-07-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-07-27 | 1995-01-26 | 1995-07-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-07-27 | 1999-01-26 | 1999-07-28 | $7700.00 | Window Closed / Lapsed |