Logic circuit with self-test

Claim 2

A logic circuit comprising: a logic section for receiving an exterior input signal and providing an exterior output signal, said logic section including a plurality of interior logic elements having corresponding input terminals and output terminals for providing interior logic signals, said input terminals and said output terminals being interconnected to perform logic operations to generate a value for said exterior output signal according to the value of said exterior input signal; and a checking circuit for receiving a control signal and the values of said interior logic signals of said output terminals of selected interior logic elements, for logically combining the value of said control signal and said received values of said interior logic signals, and for generating an error detection signal having an expected value if each of said selected logic elements is operating correctly and an error value if at least one of said selected logic elements is operating incorrectly.

Claim 3

A logic circuit according to claim 1, wherein said checking circuit comprises an exclusive OR circuit having a plurality of input terminals connected to said output terminals of said selected logic elements and to said control signal, means for computing the exclusive OR of the values of said output terminals of said selected logic elements and the control signal, and means for outputting the value of said exclusive OR computation.

Claim 4

A logic circuit according to claim 2, wherein said exclusive OR circuit comprises one exclusive OR gate with a plurality of input terminals.

Claim 5

A logic circuit comprising: a logic section for receiving an input signal and for providing an output signal, said logic section including a plurality of logic elements having corresponding input terminals and output terminals, said input terminals and said output terminals being interconnected to perform logic operations to generate a value for said output signal according to the value of said input signal; and a checking circuit for receiving a control signal and the values of said output terminals of selective logic elements, for logically combining the value of said control signal and said received values, and for generating an error detection signal having an expected value if each of said selected logic elements is operating correctly and an error value if at least one of said selected logic elements is operating incorrectly, said checking circuit comprising an exclusive OR circuit having a plurality of input terminals connected to said output terminal of said selected logic elements and to said control signal, means for computing the exlusive OR of the values of said output terminals of said selected logic elements and the control signal, and means for outputting the value of said exclusive OR computation, wherein said exclusive OR circuit comprises a plurality of exclusive OR gates connected in series, each of said exclusive OR gates having a pair of corresponding input terminals and a corresponding output terminal, the output terminal of each of said exclusive OR gates being connected to one of said input terminals of the succeeding exclusive OR gate in said series, and the second input terminal of said succeeding exclusive OR gate being connected to said output terminal of one of said selected logic elements, and a first exclusive OR gate having a first input terminal connected to said control signal, a second input terminal connected to said output terminal of one of said selected logic elements, and an output terminal connected to one of said input terminals of the first exclusive OR gate in said series.

Claim 6

A logic circuit comprising: a logic section for receiving an input signal and for providing an output signal, said logic section including a plurality of logic elements having corresponding input terminals and output terminals, said input terminals and said output terminals being interconnected to perform logic operations to generate a value for said output signal according to the value of said input signal; and a checking circuit for receiving a control signal and the values of said output terminals of selective logic elements, for logically combining the value of said control signal and said received values, and for generating an error detection signal having an expected value if each of said selected logic elements is operating correctly and an error value if at least one of said selected logic elements is operating incorrectly, said checking circuit comprising an exclusive OR circuit having a plurality of input terminals connected to said output terminal of said selected logic elements and to said control signal, means for computing the exlusive OR of the values of said output terminals of said selected logic elements and the control signal, and means for outputting the value of said exclusive OR computation, wherein said exclusive OR circuit comprises a plurality of exclusive OR gates connected in series, each of said exclusive OR gates having a pair of corresponding input terminals and a corresponding output terminal, the output terminal of each of said exclusive OR gates being connected to one of said input terminals of the succeeding exclusive OR gate in said series, and the second input terminal of said succeeding exclusive OR gate being connected to said output terminal of one of said selected logic elements, and a first exclusive OR gate having a first input terminal connected to said control signal, a second input terminal connected to said output terminal of one of said selected logic elements, and an output terminal connected to one of said input terminals of the first exclusive OR gate in said series.

Claim 7

A logic circuit according to claim 1, wherein said logic section and said checking circuit are formed on one semiconductor chip.

Claim 8

A logic circuit according to claim 1, wherein said checking circuit further comprises means for receiving said control signal and for generating an error detection signal having an expected value if said checking circuit is operating correctly and an error value if said checking circuit is operating incorrectly.

Claim 9

A logic circuit comprising a logic section for receiving an input signal and for providing an output signal, said logic section including a plurality of logic elements having corresponding input terminals and output terminals, said input terminals and said output terminals being interconnected to perform logic operations to generate a value for said output signal according to the value of said input signal; and a checking circuit for receiving a control signal, a selection signal, and the values of said output terminals of selected logic elements, for selecting one of said received values according to the value of said selection signal, for logically combining the value of said control signal and said selected received value, and for generating an output signal having a value according to said selected received value and said control signal.

Claim 10

A logic circuit comprising a logic section for receiving an input signal and for providing an output signal, said logic section including a plurality of logic elements having corresponding input terminals and output terminals, said input terminals and said output terminals being interconnected to perform logic operations to generate a value for said output signal according to the value of said input signal; and a checking circuit for receiving a control signal, a selection signal, and the values of said output terminals of selected logic elements, for selecting one of said received values according to the value of said selection signal, for logically combining the value of said control signal and said selected received value, and for generating an output signal having a value according to said selected received value and said control signal.

Claim 11

A logic circuit according to claim 7, wherein said checking circuit comprises: a decoder having a plurality of input terminals and output terminals, for receiving and decoding a selection signal on said input terminals, and generating an output signal on said output terminals with a value corresponding to the value of said selection signal; gates having corresponding first input, second input, and output terminals, said first input terminals of said gates being connected to different ones of said output terminals of said decoder, said second input terminals of said gates being connected to the output terminals of different ones of said selected logic elements; and a gate circuit having a plurality of gate circuits input terminals singly connected to different ones of said output terminals of said gates and to said control signal, for logically combining values received by said gate circuit input terminals, and for generating a signal with a value according to said logical combination.

Claim 12

A logic circuit according to claim 8, wherein said gate circuit comprises an OR circuit for generating a value corresponding to the logical OR of said control signal and the values generated on the output terminals of said gates.

Claim 13

A logic circuit according to claim 9, wherein said OR circuit is an OR gate with a plurality of input terminals.

Claim 14

A logic circuit according to claim 9, wherein said OR circuit comprises a plurality of OR gates connected in series, each of said OR gates having a pair of corresponding input terminals and a corresponding output terminal, the output terminal of each of said OR gates being connected to one of said input terminals of the succeeding OR gate in said series, and in the second input terminal of said succeeding OR gate being connected to said output terminal of one of said gates, and a first OR gate having a first input terminal connected to said control signal, a second input terminal connected to said output terminal of one of said gates, and an output terminal connected to one of said input terminals of the first OR gate in said series.

Claim 15

A logic circuit according to claim 8, wherein said gate circuit comprises an exclusive OR circuit for generating a value corresponding to the exclusive OR of said control signal and the values generated on the output terminals of said gates.

Claim 16

A logic circuit according to claim 12, wherein said exclusive OR circuit is an exclusive OR gate with a plurality of input terminals.

Claim 17

A logic circuit according to claim 12, wherein said exclusive OR circuit comprises a plurality of exclusive OR gates connected in series, each of said exclusive OR gates having a pair of corresponding input terminals and a corresponding output terminal, the output terminal of each of said exclusive OR gates being connected to one of said input terminals of the succeeding exclusive OR gate in said series, and the second input terminal of said succeeding exclusive OR gate being connected to said output terminal of one of said gates, and a first exclusive OR gate having a first input terminal connected to said control signal, a second input terminal connected to said output terminal of one of said gates, and an output terminal connected to one of said input terminals of the first exclusive OR gate in said series.

Claim 18

A logic circuit according to claim 8, wherein said gate circuit comprises an AND circuit for generating a value corresponding to the AND of said control signal and the values generated on the output terminals of said gates.

Claim 19

A logic circuit according to claim 15, wherein said AND circuit is an AND gate with a plurality of input terminals.

Claim 20

A logic circuit according to claim 15, wherein said AND circuit comprises a plurality of AND gates connected in series, each of said AND gates having a pair of corresponding input terminals and a corresponding output terminal, the output terminal of each of said AND gates being connected to one of said input terminals of the succeeding AND gate in said series and the second input terminal of said succeeding AND gate being connected to said output terminal of one of said gates, and a first AND gate having a first input terminal connected to said control signal, a second input terminal connected to said output terminal of one of said gates, and an output terminal connected to one of said input terminals of the first AND gate in said series.

Claim 21

A logic circuit according to claim 8, wherein said gates are AND gates.

Claim 22

A logic circuit according to claim 8, wherein said gates are OR gates.

Claim 23

A logic circuit according to claim 7, wherein said logic section and said checking circuit are formed on one semiconductor chip.