Digital chrominance processor with a phase and frequency controlled digital oscillator independent of the stable oscillator frequency

Claim 1

A digital chrominance signal processing circuit an input (1) of which is coupled at least via an analogue-to-digital converter (3) to an input (17) of a digital chrominance signal demodulation circuit (19) having a reference signal input (21) which, as is also a sampling signal input (23) of the analogue-to-digital converter, is coupled to an output (25) of an oscillator circuit (27) comprising a stable oscillator (65) and a digital-to-analogue converter (121) and a control signal input (89) of which is coupled to a control signal output (91) of the chrominance signal demodulation circuit, characterized in that the control signal input (89) of the oscillator circuit (27) is coupled via an adder circuit (85) to a frequency-determining input (73) of a digital oscillator (71) a clock signal input (69) of which is coupled to an output (67) of the stable oscillator (65) which is independent of the chrominance signal, whilst an output (101) of the digital oscillator (71) is coupled to the output (25) of the oscillator circuit (27) at least via the digital-to-analogue converter (121), whilst a further input (95) of the adder circuit (85) is coupled to a circuit (99) for producing a digital number which determines the quiescent frequency of the digital oscillator (71).