Standard/proportional multiplexer

Claim 2

A multiplexer system comprising, control means, register means connected to receive and store signals from said control means, counter means connected to receive signals from said register means and to supply address signals to said control means thereby to select the signal produced by said control means, user data signal supplying means for supplying data signals from user means, multiplexer means connected to said register means to receive coded signals therefrom in order to select which data signals are passed through said multiplexer means from said user data signal supplying means, clock signal supplying means, demultiplexer means connected to said register means to receive said coded signals in order to select which clock signals are generated by said demultiplexer means, data supply means connected to supply further data signals to said multiplexer means, first shift register means for operating on said further data signals in parallel or serial fashion and supplying said further data signals to said multiplexer means, and data handling means for operating upon said further data signals to supply said further data signals to said first shift register means directly or in inverse sequence.

Claim 3

The system recited in claim 1 including, pseudo-random signal generators means connected to selectively add a pseudo-random signal to the data signals which are passed through said multiplexer means.

Claim 4

The system recited in claim 1 wherein, said data handling means includes second shift register means for operating on said further data signals in parallel or serial fashion, holding register means for receiving and holding the signals produced by said second shift register means as a result of the operating on said further data signals, and second multiplexer means connected to receive said further data signals directly and to receive the signals stored in said holding register means and to selectively supply signals representative of said further data signals to said first shift register means.

Claim 5

The system recited in claim 1 wherein, said control means is connected to said first shift register means to control the loading of said further data signals into said first shift register means.

Claim 6

The system recited in claim 1 including, low rate data supplying means connected to said multiplexer means to selectively supply low rate data signals thereto.

Claim 7

The system recited in claim 1 including, synchronizer means connected to said multiplexer means to control the operation of said multiplexer in response to a sync signal from said control means.

Claim 8

The system recited in claim 1 wherein, said control means comprises a programmable memory system (PROM).

Claim 9

The system recited in claim 1 wherein, said data supply means includes phase adjustor means which permits high speed serial data input to said multiplexer means.

Claim 10

The system recited in claim 1 wherein, said data supply means includes divider means for converting the input data to a parallel mode of operation.

Claim 11

The system recited in claim 3 wherein, said first and second shift register means in said data supply means includes a parallel to serial converter register for receiving data input signals and converting said data input signals from parallel to serial format.

Claim 12

The system recited in claim 1 wherein, said control means supplies a frame signal to said counter means via said register means to reset said counter means on a periodic basis.

Claim 13

A multiplexer system comprising, control means, said control means comprises a microprocessor, counter means, decoder means connected between said microprocessor and said storage means whereby said control means can sequentially load said storage means, counter means, multiplexer means connected to said control means to selectively supply a preset count signal to said counter means from said control means, user selection means connected to receive user selection signals from said control means and to supply a selector signal to said multiplexer means thereby to establish which preset count signal is supplied to said counter means by said control means, said user selection means includes user multiplexer means connected to receive control signals from said control means, counter control means for selectively enabling said counter means to receive a new present count signal from said control means and to change the status of said user selection means, said counter control means includes logic circuitry connected between a terminal count output terminal of said counter means and a count enable input terminal of said counter means, said counter control means further includes user counter means for receiving signals from said counter means and supplying control signals to said user multiplexer means, decoder means connected to said user selection means to decode said selector signals and to supply clock signals to a selected user, and data multiplexer means connected to said user selection means to receive said selector signals thereby to select which user data bits are passed through said data multiplexer means.

Claim 14

A multiplexer system comprising, control means, said control means comprises a microprocessor, counter means, decoder means connected between said microprocessor and said storage means whereby said control means can sequentially load said storage means, counter means, multiplexer means connected to said control means to selectively supply a preset count signal to said counter means from said control means, user selection means connected to receive user selection signals from said control means and to supply a selector signal to said multiplexer means thereby to establish which preset count signal is supplied to said counter means by said control means, said user selection means includes user multiplexer means connected to receive control signals from said control means, counter control means for selectively enabling said counter means to receive a new present count signal from said control means and to change the status of said user selection means, said counter control means includes logic circuitry connected between a terminal count output terminal of said counter means and a count enable input terminal of said counter means, said counter control means further includes user counter means for receiving signals from said counter means and supplying control signals to said user multiplexer means, decoder means connected to said user selection means to decode said selector signals and to supply clock signals to a selected user, and data multiplexer means connected to said user selection means to receive said selector signals thereby to select which user data bits are passed through said data multiplexer means.

Claim 15

A multiplexer system comprising, control means, storage means connected to receive information signals from said control means in accordance with control signals supplied by said control means, said storage means comprises a temporary storage register connected to receive signals from said control means and an operational storage register connected to receive signals from said temporary storage register in response to a control signal from said control means, counter means, user control circuitry, multiplexer means for selectively transmitting information signals from said storage means to said counter means and to said user control circuitry for determining which user data shall be used thereby and which user clock pulses will be generated thereby, said multiplexer means comprises first and second multiplexer means connected to receive signals from said temporary storage register, and frame counter means connected to receive control signals from said control means and from said counter means and to supply selector signals to control the operation of said multiplexer means.

Claim 16

A multiplexer system comprising, control means, storage means connected to receive information signals from said control means in accordance with control signals supplied by said control means, said storage means comprises a temporary storage register connected to receive signals from said control means and an operational storage register connected to receive signals from said temporary storage register in response to a control signal from said control means, counter means, user control circuitry, multiplexer means for selectively transmitting information signals from said storage means to said counter means and to said user control circuitry for determining which user data shall be used thereby and which user clock pulses will be generated thereby, said multiplexer means comprises first and second multiplexer means connected to receive signals from said temporary storage register, and frame counter means connected to receive control signals from said control means and from said counter means and to supply selector signals to control the operation of said multiplexer means.

Claim 17

The system recited in claim 13 wherein, said storage means comprises buffer register circuit means.

Claim 18

The system recited in claim 13 wherein, said multiplexer means further includes, data multiplexer means for selectively passing data signals therethrough, and clock decoder means for selectively generating clock signals, wherein each of said data multiplexer means, said clock decoder means and said first multiplexer means connected to receive output signals produced by said second multiplexer means.