US4680755A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Real-time end of packet signal generator
Assignee: HP Inc
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Filing: 1985-11-14
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Granted: 1987-07-14
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Expires: 2005-11-14
Abstract
Abstract Provided is a circuit for signalling the real-time end of a local area network packet as the packet is being pulled off a transmission medium and stored in memory. Storage of the packet is performed by a local area network coprocessor. The circuit monitors for the simultaneous occurrence of three conditions: the coprocessor is in a write-to-memory cycle; it is writing to the address of a status word pertaining to a packet; and the most significant bit of the status word is being set. If all three conditions are true, the circuit asserts the real-time end-of-packet signal.
Inventors
- 👤 Stephen P. Reames
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 20:21
CPC Classifications
H; H04; H04L; H04L12/00; H04L12/28; H04L12/40; H04L12/40006; H04L12/40032; H04L12/407; H04L12/413; H04L43/00; H04L12/40026; H04L43/18
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
272 words
An apparatus for generating an end-of-packet signal, said end-of-packet signal indicating, in real time, the occurrence, of the tail end of a local area network packet, said packet being transmitted on a local area network, said apparatus comprising: a local area network coprocessor, said coprocessor being resident in a host device, said host device having memory and a memory address bus, said coprocessor being adapted to receive local area network packets in bit serial form from a local area network transmission medium, to store said packets in host device memory in a uniform structured format, to create and maintain an associated status word for each stored packet, the most significant bit of each said status word being set to true when the end of said packet is received, and to generate a write-strobe-signal whenever said coprocessor is in a write-to-memory cycle; a memory-address-comparison means for comparing the address in host device memory to which said coprocessor is writing with addresses of said status words, and for generating an output signal when the address in host device memory being written to by said coprocessor is the address of one of said status words; an electronic logic gate having as inputs said output signal of said memory-address-comparison means and the most significant data-bit of data words written to said memory of said host device, said electronic logic gate producing a true output when both of said inputs are true; and a clocked flip-flop circuit, having as input the output of said electronic logic gate, and having as clock signal the write-strobe-signal of said coprocessor, said clocked flip-flop circuit producing as output said end-of-packet signal.
Claim 2
Independent Claim
272 words
An apparatus for generating an end-of-packet signal, said end-of-packet signal indicating, in real time, the occurrence, of the tail end of a local area network packet, said packet being transmitted on a local area network, said apparatus comprising: a local area network coprocessor, said coprocessor being resident in a host device, said host device having memory and a memory address bus, said coprocessor being adapted to receive local area network packets in bit serial form from a local area network transmission medium, to store said packets in host device memory in a uniform structured format, to create and maintain an associated status word for each stored packet, the most significant bit of each said status word being set to true when the end of said packet is received, and to generate a write-strobe-signal whenever said coprocessor is in a write-to-memory cycle; a memory-address-comparison means for comparing the address in host device memory to which said coprocessor is writing with addresses of said status words, and for generating an output signal when the address in host device memory being written to by said coprocessor is the address of one of said status words; an electronic logic gate having as inputs said output signal of said memory-address-comparison means and the most significant data-bit of data words written to said memory of said host device, said electronic logic gate producing a true output when both of said inputs are true; and a clocked flip-flop circuit, having as input the output of said electronic logic gate, and having as clock signal the write-strobe-signal of said coprocessor, said clocked flip-flop circuit producing as output said end-of-packet signal.
Claim 3
Dependent Claim
78 words
An apparatus as in claim 1 wherein the memory-address-comparison means comprises a look-up read only memory, said read only memory having address select lines which read on the memory address bus of said host device such that whatever address signals are placed on said address bus will drive said address select lines, said read only memory being configured to produce a true output when the address of one of said status words is placed on said address bus.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-07-13 | 1991-01-12 | 1991-07-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-07-13 | 1995-01-12 | 1995-07-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-07-13 | 1999-01-12 | 1999-07-14 | $7700.00 | Window Closed / Lapsed |