Semiconductor integrated circuit device

Claim 2

A semiconductor integrated circuit device which includes memory cells that need to be periodically refreshed, and which includes means for performing an inspection step which examines refresh characteristics and means for generating a signal for use in determining a refresh period, said semiconductor integrated circuit device comprising: a timer circuit which generates output signals for determining a refresh timing of said memory cells and which comprises a program circuit which changes the period of said output signals according to said signal.

Claim 3

A semiconductor integrated circuit device according to claim 1, wherein said timer circuit has a gate circuit to control the generation of said output signals.

Claim 4

A semiconductor integrated circuit device according to claim 2, wherein said program circuit comprises a nonvolatile memory element that can be programmed.

Claim 5

A semiconductor integrated circuit device according to claim 3, wherein said program circuit comprises a fuse element and a resistance element connected in series therewith.

Claim 6

A semiconductor integrated circuit device according to claim 2, further comprising an address counter which forms address signals corresponding to said memory cells.

Claim 7

A semiconductor integrated circuit device according to claim 5, wherein said address counter receives the signals produced from said timer as incrementing pulses.

Claim 8

A semiconductor integrated circuit device according to claim 6, wherein said program circuit comprises a nonvolatile memory element that can be programmed.

Claim 9

A semiconductor integrated circuit device according to claim 7, wherein said program circuit comprises a fuse element and a resistance element connected in series therewith.

Claim 10

A semiconductor integrated circuit device comprising: a first switching element which permits the flow of charging current to a capacitor; a second switching element which forms a discharge path for said capacitor; means coupled to said first and second switching elements for driving said first and second switching elements so that said first and second switching elements are rendered conductive at timings different from each other; a first variable impedance element connected in series with said second switching element; a program element coupled to said first variable impedance element for determining the impedance of said first variable impedance element; and a level detector circuit which detects the level of voltage of said capacitor.

Claim 11

A semiconductor integrated circuit device comprising: a first switching element which permits the flow of charging current to a capacitor; a second switching element which forms a discharge path for said capacitor; means coupled to said first and second switching elements for driving said first and second switching elements so that said first and second switching elements are rendered conductive at timings different from each other; a first variable impedance element connected in series with said second switching element; a program element coupled to said first variable impedance element for determining the impedance of said first variable impedance element; and a level detector circuit which detects the level of voltage of said capacitor.

Claim 12

A semiconductor integrated circuit device according to claim 9, wherein said means comprises a feedback circuit which controls the operation of each of said first and second switching elements based upon the output of said level detector circuit.

Claim 13

A semiconductor integrated circuit device according to claim 10, wherein each of said first and second switching elements, and said first variable impedance element comprises an MOSFET.

Claim 14

A semiconductor integrated circuit device according to claim 11, wherein said first variable impedance element is connected in parallel with a second variable impedance element of which the switching function is controlled in synchronism with said second switching element.

Claim 15

A semiconductor integrated circuit device comprising: a plurality of dynamic memory cells that must be periodically refreshed; a decoder circuit for selecting said memory cells; an address buffer; and a refresh control circuit which comprises: a program circuit which comprises a program element and which generates an output signal according to the condition of said program element; a timer circuit coupled to said program circuit for producing output signals whose pulse period varies depending upon said output signal of said program circuit; an address counter which counts the output signals of said timer circuit to form an address signal; and means for forming a control signal which controls a multiplexer; wherein said multiplexer is coupled to said refresh circuit for supplying to said decoder circuit the address signal produced either by said address buffer or by said address counter in accordance with said control signal, so that said multiplexer supplies to said decoder circuit the address signal produced by said address counter when the dynamic memory cells specified by said address counter are refreshed.

Claim 16

A semiconductor integrated circuit device comprising: a plurality of dynamic memory cells that must be periodically refreshed; a decoder circuit for selecting said memory cells; an address buffer; and a refresh control circuit which comprises: a program circuit which comprises a program element and which generates an output signal according to the condition of said program element; a timer circuit coupled to said program circuit for producing output signals whose pulse period varies depending upon said output signal of said program circuit; an address counter which counts the output signals of said timer circuit to form an address signal; and means for forming a control signal which controls a multiplexer; wherein said multiplexer is coupled to said refresh circuit for supplying to said decoder circuit the address signal produced either by said address buffer or by said address counter in accordance with said control signal, so that said multiplexer supplies to said decoder circuit the address signal produced by said address counter when the dynamic memory cells specified by said address counter are refreshed.