US4679216A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Synchronous binary counter
Assignee: Toshiba Corp
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Filing: 1986-08-07
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Granted: 1987-07-07
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Expires: 2006-08-07
Abstract
Abstract A synchronous binary circuit comprising a counter including J-K flip-flops constituting lower l bit stages and higher m bit stages, first logic means for feeding, to J and K input terminals on each of flip-flops among the lower l bit stage flip-flops higher than the second bit stage, an AND of non-inverted outputs of all the lower stage flip-flops than the pertinent stage, second logic means for feeding, to the J and K input terminals of the first stage flip-flops among the higher m bit stage flip-flops, a first logical product of the non-inverted output of a one bit lower stage flip-flop and non-inverted outputs of the first to (l-1)-th bit stage flip-flops among the lower bit stage flip-flops, and third logic means for feeding, to the J and K input terminals of flip-flops among the higher m bit stage flip-flops higher than the second stage, a second logical product of non-inverted outputs of the lower first to (l-1)-th bit stage flip-flops and a third logical product, the third logical product being a logical product of an non-inverted output of a flip-flop lower by one bit than each of the flip-flops lower than the second stage and a fourth logical product, and the fourth logical product being a logical product of non-inverted outputs of flip-flops lower by more than two bit stages in the higher bit stage flip-flops.
Inventors
- 👤 Tetsuya Iida
- 👤 Takayoshi Ikarashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 14:54
CPC Classifications
H; H03; H03K; H03K23/00; H03K23/40; H03K23/50
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
243 words
A synchronous binary counter comprising: a counter including J-K flip-flops constituting lower l bit stages and higher m bit stages, a common clock pulse being fed to a clock terminal of each of said flip-flops; first logic means for feeding, to J and K input terminals of each of flip-flops among said lower l bit stage flip-flops higher than the second bit stage, an AND of non-inverted outputs of all the lower stage flip-flops than the pertinent stage; second logic means for feeding, to the J and K input terminals of the first stage flip-flops among said higher m bit stage flip-flops, a first logical product of the non-inverted output of a one bit lower stage flip-flop and non-inverted outputs of the first to (l-1)-th bit stage flip-flops among said lower bit stage flip-flops; and third logic means for feeding, to the J and K input terminals of flip-flops among said higher m bit stage flip-flops higher than the second stage, a second logical product of non-inverted outputs of the lower first to (l-1)-th bit stage flip-flops and a third logical product, said third logical product being a logical product of an non-inverted output of a flip-flop lower by one bit than each of said flip-flops lower than the second stage and a fourth logical product, and said fourth logical product being a logical product of non-inverted outputs of flip-flops lower by more than two bit stages in said higher bit stage flip-flops.
Claim 2
Dependent Claim
243 words
A synchronous binary counter comprising: a counter including J-K flip-flops constituting lower l bit stages and higher m bit stages, a common clock pulse being fed to a clock terminal of each of said flip-flops; first logic means for feeding, to J and K input terminals of each of flip-flops among said lower l bit stage flip-flops higher than the second bit stage, an AND of non-inverted outputs of all the lower stage flip-flops than the pertinent stage; second logic means for feeding, to the J and K input terminals of the first stage flip-flops among said higher m bit stage flip-flops, a first logical product of the non-inverted output of a one bit lower stage flip-flop and non-inverted outputs of the first to (l-1)-th bit stage flip-flops among said lower bit stage flip-flops; and third logic means for feeding, to the J and K input terminals of flip-flops among said higher m bit stage flip-flops higher than the second stage, a second logical product of non-inverted outputs of the lower first to (l-1)-th bit stage flip-flops and a third logical product, said third logical product being a logical product of an non-inverted output of a flip-flop lower by one bit than each of said flip-flops lower than the second stage and a fourth logical product, and said fourth logical product being a logical product of non-inverted outputs of flip-flops lower by more than two bit stages in said higher bit stage flip-flops.
Claim 3
Dependent Claim
30 words
The synchronous binary counter according to claim 1, wherein said individual bit stages each include means for inverting the inverted output of each stage flip-flop to provide a non-inverted output.
Claim 4
Dependent Claim
50 words
The synchronous binary counter according to claim 1, wherein said l and m are both 4, and said third logic circuit includes first, second and third input means for feeding said last recited AND to the second, third and fourth bit stage flip-flops among said higher four bit stage flip-flops.
Claim 5
Dependent Claim
108 words
The synchronous binary counter according to claim 3, wherein said first input means includes a first NAND gate for ANDing a non-inverted output of the highest bit stage flip-flop among said lower bit stage flip-flops and a non-inverted output of the first bit stage flip-flop among said higher bit stage flip-flops and a second AND gate for ANDing the AND output of said first AND gate and non-inverted outputs of the first to third bit stage flip-flops among said lower bit stage flip-flops and feeding the resultant AND output to the J and K input terminals of the second bit stage flip-flops among said higher bit stage flip-flops.
Claim 6
Dependent Claim
85 words
The synchronous binary counter according to claim 4, wherein said second input means includes a third AND gate for ANDing the AND output of said first AND gate and a fourth AND gate for ANDing the AND output of said third AND gate and non-inverted outputs of the first to third bit stage flip-flops among said lower bit stage flip-flops and feeding the resultant AND output to the J and K input terminals of the third bit stage flip-flop among said upper bit stage flip-flops.
Claim 7
Dependent Claim
100 words
The synchronous binary counter according to claim 5, wherein said third input means includes a fifth AND gate for ANDing the AND output of said third AND gate and the non-inverted output of said third bit stage flip-flop among said higher bit stage flip-flops and a sixth AND gate for ANDing the AND output of said fifth AND gate and the non-inverted outputs of the first to third flip-flops among said lower bit stage flip-flops and feeding the resultant AND output to the J and K input terminals of the fourth bit stage flip-flop among said higher bit stage flip-flops.
Claim 8
Dependent Claim
104 words
The synchronous binary counter according to claim 3, wherein said first input means includes a first NAND gate for NANDing the non-inverted output of the highest bit stage flip-flop among said lower bit stage flip-flops, an inverter for inverting the level of the NAND output of said NAND gate and a second NAND gate for NANDing the output of said inverter and the non-inverted output of the first to third bit stage flip-flops among said lower bit stage flip-flops and feeding the resultant NAND output to the J and K input terminals of the second bit stage flip-flop among said higher bit stage flip-flops.
Claim 9
Dependent Claim
100 words
The synchronous binary counter according to claim 1, wherein said second input means includes a NOR gate for NORing the NAND output of said first NAND gate and the inverted output of the second bit stage flip-flop among said higher bit stage flip-flops, and a third NAND gate for NANDing the NOR output of said NOR gate and the non-inverted outputs of the first to third bit stage flip-flops among said lower bit stage flip-flops and feeding the resultant NAND output to the J and K input terminals of the third bit stage flip-flop among said higher bit stage flip-flops.
Claim 10
Dependent Claim
112 words
The synchronous binary counter according to claim 8, wherein said third input means includes a fourth NAND gate for NANDing the NOR output of said NOR gate and the non-inverted output of said third bit stage flip-flop among said higher bit stage flip-flops, an inverter for inverting the level of the output of said fourth NAND gate, and a fifth NAND gate for NANDing the output of said inverter and the non-inverted outputs of the first to third bit stage flip-flops among said lower bit stage flip-flops and feeding the resultant NAND output to the J and K input terminals of the fourth bit stage flip-flop among said higher bit stage flip-flops.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-07-06 | 1991-01-05 | 1991-07-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-07-06 | 1995-01-05 | 1995-07-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-07-06 | 1999-01-05 | 1999-07-07 | $7700.00 | Window Closed / Lapsed |