US4679195A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Error tracking apparatus in a data processing system
Assignee: Fujitsu IT Holdings Inc
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Filing: 1985-04-10
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Granted: 1987-07-07
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Expires: 2005-04-10
Abstract
Abstract Disclosed is an error tracking apparatus for a data processing system having a plurality of data locations. At each data location at which an error is to be detected, an error detection means is provided for generating an error signal upon the detection error. Associated each error detection means is a counter means for counting system cycles and storing a system cycle count. Upon the generation of an error signal, the counter means stops counting, thereby freezing the system cycle count at a value corresponding to the occurrence of the error. The error signal is propagated through the system to generate a machine check which disables the system clock, thereby stopping the balance of the counter means at some cycle subsequent to the first detection of the error. By interrogation the system cycle counts stored in each of the counter means, an error history can be determined for the data processing system.
Inventors
- 👤 Loren G. Dewey
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 04:17
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0706; G06F11/0721; G06F11/079
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
202 words
In a data processing system, including a plurality of data locations, through which data are propagated in system clock cycles in response to a system clock signal, an error tracking apparatus comprising: a plurality of error detection means, each in communication with an associated data location, for detecting errors in the associated location and for generating an error signal upon detection of an error; a plurality of counter means, each in communication with an associated error detection means and responsive to the system clock signal, for counting system clock cycles and storing a system cycle count for the data location associated with the respective error detection means, each of said counter means including means, responsive to an error signal from the associated error detection means, for disabling the counter means to freeze the system cycle count indicating the system clock cycle during which the error signal was generated; interrupt means, responsive to the error signals, for disabling the system clock signal, whereby the system cycle count in each of said plurality of counter means is indicative of the system clock cycle during which the system clock signal was disabled, or during which an error signal was generated at its associated data location.
Claim 2
Dependent Claim
202 words
In a data processing system, including a plurality of data locations, through which data are propagated in system clock cycles in response to a system clock signal, an error tracking apparatus comprising: a plurality of error detection means, each in communication with an associated data location, for detecting errors in the associated location and for generating an error signal upon detection of an error; a plurality of counter means, each in communication with an associated error detection means and responsive to the system clock signal, for counting system clock cycles and storing a system cycle count for the data location associated with the respective error detection means, each of said counter means including means, responsive to an error signal from the associated error detection means, for disabling the counter means to freeze the system cycle count indicating the system clock cycle during which the error signal was generated; interrupt means, responsive to the error signals, for disabling the system clock signal, whereby the system cycle count in each of said plurality of counter means is indicative of the system clock cycle during which the system clock signal was disabled, or during which an error signal was generated at its associated data location.
Claim 3
Dependent Claim
36 words
The apparatus of claim 1, further including: scan out means for providing a data path for interrogation of the system cycle counts stored in the plurality of counter means upon disabling of the system clock signal.
Claim 4
Dependent Claim
27 words
The apparatus of claim 1, wherein: said interrupt means disables the system clock signal in the same system cycle at all of said plurality of counter means.
Claim 5
Dependent Claim
32 words
The apparatus of claim 1, wherein: said means for disabling the counter means is operable to freeze the system cycle count in the same cycle as the associated error signal is generated.
Claim 6
Dependent Claim
46 words
The apparatus of claim 1, wherein said plurality of data locations are organized into sections within the data processing system and further including; means for combining error signals generated from data locations within a given section to generate a process damage signal for the given section.
Claim 7
Dependent Claim
84 words
The apparatus of claim 5, further including: a plurality of counter means, each in communication with an associated section and responsive to the system clock signal, for counting system cycles and storing a system cycle count for the associated section, each of said counter means including means, responsive to a process damage signal from the associated section, for disabling the counter means to freeze the system cycle count indicating the system cycle during which a process damage signal was generated at the associated section.
Claim 8
Dependent Claim
74 words
The apparatus of claim 6, wherein said sections are organized into blocks of sections and further including: a plurality of means, each associated with a given block and connected to receive the process damage signals from sections within the given block, for combining the received process damage signals to generate a block-level process damage signal; and wherein said interrupt means includes means responsive to the block-level process damage signals for disabling the system clock.
Claim 9
Dependent Claim
190 words
In a data processing system that includes a plurality of data registers through which data words are propagated in system cycles during processing according to a system clock signal, and a system clock generating the system clock signal responsive to a disable signal for stopping the system clock signal, an apparatus for tracking errors comprising: a plurality of error detection means, each in communication with one of the data registers and responsive to the data word in the one data register during a system cycle, for detecting errors at the one data register and generating an error signal if an error is detected; a plurality of counter means, each in communication with one of the error detection means and receiving the system clock signal, for generating and storing a system cycle count in response to the system clock signal, each of the counter means including means, connected to receive the error signal from the one error detection means, for freezing the system cycle count upon receipt of the error signal; means, in communication with the plurality of error detection means, responsive to the error signals for generating the disable signal.
Claim 10
Dependent Claim
190 words
In a data processing system that includes a plurality of data registers through which data words are propagated in system cycles during processing according to a system clock signal, and a system clock generating the system clock signal responsive to a disable signal for stopping the system clock signal, an apparatus for tracking errors comprising: a plurality of error detection means, each in communication with one of the data registers and responsive to the data word in the one data register during a system cycle, for detecting errors at the one data register and generating an error signal if an error is detected; a plurality of counter means, each in communication with one of the error detection means and receiving the system clock signal, for generating and storing a system cycle count in response to the system clock signal, each of the counter means including means, connected to receive the error signal from the one error detection means, for freezing the system cycle count upon receipt of the error signal; means, in communication with the plurality of error detection means, responsive to the error signals for generating the disable signal.
Claim 11
Dependent Claim
116 words
The apparatus of claim 8, wherein the data registers are organized in sections of the data processing machine, further including a plurality of means, each in communication with the error detection means for data registers within one section of the system, for combining the error signals from the one section to generate a section-level process damage signal; and a plurality of section-level counter means, each connected to receive one section-level process damage signal and receiving the system clock signal, for generating and storing a system cycle count in response to the system clock signal, each of the counter means including means for freezing the system cycle count upon receipt of the one section-level process damage signal.
Claim 12
Dependent Claim
79 words
The apparatus of claim 9, wherein the sections are organized into blocks of sections and further including: a plurality of means, each associated with a given block and connected to receive the section-level process damage signals from sections within the given block, for combining the section-level process damage signals to generate a block-level process damage signal; and the means for generating the disabled signal includes means for combining the block-level process damage signals for supply as the disable signal.
Claim 13
Dependent Claim
39 words
The apparatus of claim 8, wherein the data words include data and an error code for the data and the error detection means include means responsive the the data and the error code for detecting errors in the data.
Claim 14
Dependent Claim
13 words
The apparatus of claim 11, wherein the error code is a parity bit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-07-06 | 1991-01-05 | 1991-07-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-07-06 | 1995-01-05 | 1995-07-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-07-06 | 1999-01-05 | 1999-07-07 | $7700.00 | Window Closed / Lapsed |