US4678937A
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Electrical isolation circuit
Assignee: Emerson Process Management Ltd
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Filing: 1984-02-03
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Granted: 1987-07-07
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Expires: 2004-02-03
Abstract
Abstract A circuit provides electrical isolation from an input signal which has a leading edge and a trailing edge. On the leading edge of the input signal, a first signal is transmitted across an isolation device to provide a first isolated signal representative of the leading edge of the input signal. On the trailing edge of the input signal, a second signal is transmitted across the isolation device to provide a second isolated signal representative of the trailing edge of the input signal. The first and second isolated signals are electrically isolated from and representative of the input signal.
Inventors
- 👤 Timothy D. Price
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 08:22
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
169 words
An isolator circuit for providing dielectric isolation for an input signal which has a leading edge and a trailing edge spaced apart in time, the circuit comprising: first means for receiving the input signal and for providing a first signal representative of the leading edge of the input signal and for providing a second signal representative of the trailing edge of the input signal; and isolation means having an isolation input coupled to the first means and having a single isolation output for providing a first isolated signal representative of the leading edge of the input signal and a second isolated signal representative of the trailing edge of the input signal and distinct from the first isolated signal, the isolation means providing signal transmission and dielectric isolation between the isolation input and the isolation output such that the first and second isolated signals are dielectrically isolated from the input signal and the time spacing between the leading edge and the trailing edges is substantially preserved in the isolation output.
Claim 2
Dependent Claim
169 words
An isolator circuit for providing dielectric isolation for an input signal which has a leading edge and a trailing edge spaced apart in time, the circuit comprising: first means for receiving the input signal and for providing a first signal representative of the leading edge of the input signal and for providing a second signal representative of the trailing edge of the input signal; and isolation means having an isolation input coupled to the first means and having a single isolation output for providing a first isolated signal representative of the leading edge of the input signal and a second isolated signal representative of the trailing edge of the input signal and distinct from the first isolated signal, the isolation means providing signal transmission and dielectric isolation between the isolation input and the isolation output such that the first and second isolated signals are dielectrically isolated from the input signal and the time spacing between the leading edge and the trailing edges is substantially preserved in the isolation output.
Claim 3
Dependent Claim
25 words
The circuit of claim 1 wherein the first means provides the first signal proximate in time to receiving the leading edge of the input signal.
Claim 4
Dependent Claim
33 words
The circuit of claim 2 wherein the time between the first means receiving the leading edge and providing the first signal is relatively constant for immediately successive leading edges of the input signal.
Claim 5
Dependent Claim
25 words
The circuit of claim 1 wherein the first means provides the second signal proximate in time to receiving the trailing edge of the input signal.
Claim 6
Dependent Claim
33 words
The circuit of claim 4 wherein the time between the first means receiving the trailing edge and providing the second signal is relatively constant for immediately successive trailing edges of the input signal.
Claim 7
Dependent Claim
61 words
The circuit of claim 2 wherein the first means provides the second signal proximate in time to receiving the trailing edge of the input signal and wherein the time between the first means receiving the leading edge and providing the first signal and the time between the first means receiving the trailing edge and providing the second signal is substantially equal.
Claim 8
Dependent Claim
20 words
The circuit of claim 1 wherein the input signal alternately comprises a first high voltage and a first low voltage.
Claim 9
Dependent Claim
32 words
The circuit of claim 7 and further comprising a readout means coupled to the output of the isolation means for providing an output signal isolated from and representative of the input signal.
Claim 10
Dependent Claim
32 words
The circuit of claim 8 wherein the output signal alternately comprises a second high voltage and a second low voltage representative of and electrically isolated from the first high and low voltages.
Claim 11
Dependent Claim
34 words
The circuit of claim 9 wherein the difference between the first high voltage and the first low voltage is substantially equal to the difference between the second high voltage and the second low voltage.
Claim 12
Dependent Claim
62 words
The circuit of claim 1 and further comprising: load means for receiving an input current and providing a first input signal level; ramp means for providing a ramp signal; and comparator means coupled to the load means and to the ramp means for comparing the first input signal level to the ramp signal and providing the input signal as a function thereof.
Claim 13
Dependent Claim
27 words
The circuit of claim 11 and further comprising squaring means coupled between the comparator means and the first means for squaring the edges of the input signal.
Claim 14
Dependent Claim
37 words
The circuit of claim 11 wherein the input current comprises a 4 to 20 milliampere signal, the load means comprises a 250 ohm resistor and the first input signal level comprises a 1 to 5 volt signal.
Claim 15
Dependent Claim
25 words
The circuit of claim 1 wherein the first signal comprises a first pulse having distinct characteristics representative of the leading edge of the input signal.
Claim 16
Dependent Claim
30 words
The circuit of claim 14 wherein the first isolated signal comprises a pulse having distinct characteristics representative of the leading edge of the input signal responsive to the first pulse.
Claim 17
Dependent Claim
31 words
The circuit of claim 1 wherein the second signal comprises a second pulse having distinct characteristics different from the first signal characteristics representative of the trailing edge of the input signal.
Claim 18
Dependent Claim
30 words
The circuit of claim 16 wherein the second isolated signal comprises a pulse having distinct characteristics representative of the trailing edge of the input signal responsive to the second pulse.
Claim 19
Dependent Claim
32 words
The circuit of claim 1 wherein the first signal comprises a first pulse having a first pulse duration and wherein the second signal comprises a second pulse having a second pulse duration.
Claim 20
Dependent Claim
27 words
The circuit of claim 18 wherein one of the first and second pulse durations is longer than the other one of the first and second pulse durations.
Claim 21
Dependent Claim
29 words
The circuit of claim 18 wherein the first and second isolated signals comprise respective first and second isolated pulses having durations representative of the first and second pulse durations.
Claim 22
Dependent Claim
34 words
The circuit of claim 20 wherein the first pulse duration is substantially equal to the first isolated pulse duration and wherein the second pulse duration is substantially equal to the second isolated pulse duration.
Claim 23
Dependent Claim
44 words
The circuit of claim 20 and further comprising readout means for receiving the first and second isolated pulses and providing an output pulse width modulated signal having a leading edge and a trailing edge as a function of the first and second isolated pulses.
Claim 24
Dependent Claim
66 words
The circuit of claim 22 wherein the readout means comprises flipflop means for receiving the first and second isolated pulses and providing the leading edge of the output pulse width modulated signal as a function of the first isolated pulse and the trailing edge as a function of the second isolated pulse based on the time between and durations of the first and second isolated pulses.
Claim 25
Dependent Claim
157 words
An electrical isolation circuit for providing insulating isolation for an input signal which has a leading edge and a trailing edge spaced apart in time, the circuit comprising: first means for receiving the input signal and providing a first signal representative of the leading edge of the input signal and for providing a second signal representative of the trailing edge of the input signal; light emitting means having an isolation input for receiving the first and second signals and having a single light emitter which emits light signals responsive to the first and second signals; and light responsive means electrically insulated from the light emitting means and optically coupled to the light emitting means for receiving the emitted light signals and providing a first isolated signal and a second isolated signal responsive to the received light signal such that the spacing between the leading and trailing edges is substantially preserved in the first and second isolated signals.
Claim 26
Dependent Claim
157 words
An electrical isolation circuit for providing insulating isolation for an input signal which has a leading edge and a trailing edge spaced apart in time, the circuit comprising: first means for receiving the input signal and providing a first signal representative of the leading edge of the input signal and for providing a second signal representative of the trailing edge of the input signal; light emitting means having an isolation input for receiving the first and second signals and having a single light emitter which emits light signals responsive to the first and second signals; and light responsive means electrically insulated from the light emitting means and optically coupled to the light emitting means for receiving the emitted light signals and providing a first isolated signal and a second isolated signal responsive to the received light signal such that the spacing between the leading and trailing edges is substantially preserved in the first and second isolated signals.
Claim 27
Dependent Claim
117 words
A circuit for providing electrical insulating isolation between an input signal and an output signal, the circuit comprising: isolation means having an isolation input and a single isolation output for providing electrical insulating isolation and signal transmission between the isolation input and the isolation output; first means having an input for receiving the input signal and having an output coupled to the isolation input, said first means providing a first pulse and a second pulse at its output, the first and second pulses having a time relationship representative of the input signal; and output means coupled to the isolation output for providing the output signal such that the time relationship is substantially preserved in the output signal.
Claim 28
Dependent Claim
117 words
A circuit for providing electrical insulating isolation between an input signal and an output signal, the circuit comprising: isolation means having an isolation input and a single isolation output for providing electrical insulating isolation and signal transmission between the isolation input and the isolation output; first means having an input for receiving the input signal and having an output coupled to the isolation input, said first means providing a first pulse and a second pulse at its output, the first and second pulses having a time relationship representative of the input signal; and output means coupled to the isolation output for providing the output signal such that the time relationship is substantially preserved in the output signal.
Claim 29
Dependent Claim
37 words
The circuit of claim 25 wherein the isolation means further comprises means coupled to the first means for providing a signal coincident with the first pulse such that the first pulse is distinguished from the second pulse.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-07-06 | 1991-01-05 | 1991-07-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-07-06 | 1995-01-05 | 1995-07-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-07-06 | 1999-01-05 | 1999-07-07 | $7700.00 | Window Closed / Lapsed |