Computer graphics system with low memory enhancement circuit

Claim 3

image source means for providing the ancillary data, and for providing the base pixel data in a serial stream in sequential order of display to define an image raster display having X pixels in each of Y scanlines; each pixel of the base pixel data having M bits of binary data with 2-to-the M binary codes at least one of which is an ancillary code; ancllary code detector responsive to the base pixel data in the serial stream of pixel data for detecting the at least one ancillary code therein; code counter means responsive to the ancillary code detector for providing a sequence of ancillary addresses each having A bits therein, each of the A bits of address having a most significant portion of Am bits and a least significant portion of Al bits; and ancillary memory containing L locations with E bits of memory at each location for storing the ancillary data provided by the image source means, and responsive to the ancillary addresses from the code counter means for providing the composite pixel data to the monitor, the Am bits of address access Lm major memory units within the ancillary memory, and the Al bits of address access Ll subunits of memory within each of the Lm major memory units, the access time required for the Al portion to address a memory subunit in the ancillary memory is shorter than the access time required for the full A bits to address a memory subunit in the ancillary memory.

Claim 4

image source means for providing the ancillary data, and for providing the base pixel data in a serial stream in sequential order of display to define an image raster display having X pixels in each of Y scanlines; each pixel of the base pixel data having M bits of binary data with 2-to-the M binary codes at least one of which is an ancillary code; ancllary code detector responsive to the base pixel data in the serial stream of pixel data for detecting the at least one ancillary code therein; code counter means responsive to the ancillary code detector for providing a sequence of ancillary addresses each having A bits therein, each of the A bits of address having a most significant portion of Am bits and a least significant portion of Al bits; and ancillary memory containing L locations with E bits of memory at each location for storing the ancillary data provided by the image source means, and responsive to the ancillary addresses from the code counter means for providing the composite pixel data to the monitor, the Am bits of address access Lm major memory units within the ancillary memory, and the Al bits of address access Ll subunits of memory within each of the Lm major memory units, the access time required for the Al portion to address a memory subunit in the ancillary memory is shorter than the access time required for the full A bits to address a memory subunit in the ancillary memory.

Claim 5

The apparatus of claim 1, wherein the image source means further comprises a pixel memory means.

Claim 6

The apparatus of claim 2, wherein the pixel memory means is a pixel bit map memory of the displayed image having X-Y locations.

Claim 7

The apparatus of claim 3 wherein the bit map memory map holds one raster frame of base pixel data.

Claim 8

The apparatus of claim 3, further comprising a sequential pixel address means for sequentially accessing the base pixel data in the bit map memory to form the serial stream of base pixel data.

Claim 9

The apparatus of claim 5, wherein the sequential pixel address means is a pixel clock.

Claim 10

The apparatus of claim 1, wherein Am bits+Al bits=A bits, and (Lm locations)×(Ll locations)=L locations.

Claim 11

The apparatus of claim 1, wherein Al bits=1 bit, and A bits=Am bits+1 bit.

Claim 12

The apparatus of claim 1, wherein the ancillary code counter and the ancillary memory are operated in a frame mode permitting 2-to-the-A changes in ancillary data per display frame.

Claim 13

The apparatus of claim 1, wherein the ancillary code counter and the ancillary memory are operated in a scanline mode in which each scanline is allocated 2-to-the-A divided by Y locations in the ancillary memory, permitting 2-to-the-A divided by Y changes in ancillary data per scanline frame.

Claim 14

The apparatus of claim 1, wherein the scanlines in the middle region of the display are allocated more locations in the ancillary memory than the scanlines in the upper and lower regions of the display, and the ancillary code counter and the ancillary memory are operated in a differential change density mode in which the scanlines in the middle region of the display are permitted higher ancillary change densities.

Claim 15

The apparatus of claim 1, wherein the allocation of ancillary memory locations per scanline progressively increases toward the center of the display, and the ancillary code counter and the ancillary memory are operated in a differential change density mode in which the ancillary change density progressively increases toward the middle of the display.

Claim 16

The apparatus of claim 1, wherein the M bits of base pixel data in the XY image source means is edge data for the faces in the displayed image.

Claim 17

The apparatus of claim 13, wherein M=1 and the ancillary codes are "0" and "1".

Claim 18

The apparatus of claim 14, wherein the ancillary code detector is responsive to the transition from 0-to-1 and the transition from 1-to-0 for incrementing the ancillary address means.

Claim 19

The apparatus of claim 15, wherein all of the bits of edge data between each 0-to-1 transition and the subsequent 1-to-0 transition are "1"s, and all of the bits of edge data between 1-to-0 transition and the subsequent 0-to-1 transition are "0"s.

Claim 20

The apparatus of claim 14, wherein the ancillary code detector is a transition detector for detecting face edges in the edge data stream.

Claim 21

The apparatus of claim 17, wherein the code counter means comprises: a counter for counting every other edge transition in the edge data stream to provide the most significant A minus one bits of the A bit address to the ancillary memory for accessing the major unit of memory therein; and a one bit counter for detecting every edge transition in the edge data stream to provide the LSB of the A bit address to the ancillary memory for accessing one of two memory subunits Lf and Lb within each major memory unit.

Claim 22

The apparatus of claim 18, wherein at least a portion of the Lf memory subunits contain display data for a foreground face.

Claim 23

The apparatus of claim 19, wherein the Lf subunits are accessed by the full A bit address in time Tf, and the Lb subunits are accessed by the LSB of the address in time Tb.

Claim 24

The apparatus of claim 20, wherein Tb is less than Tf.

Claim 25

The apparatus of claim 21, wherein the current display face associated with the currently accessed memory subunit in the ancillary memory is displayed on the monitor and terminated when the next subunit is accessed providing the next display face.

Claim 26

The apparatus of claim 22, wherein access time Tb requires Pf pixel periods and is the minimum number of display pixels for a foreground face, and the access time Tf requires Pb pixel periods and is the minimum number of display pixels for a background face.

Claim 27

The apparatus of claim 23, wherein Pf is one pixel.

Claim 28

The apparatus of claim 23, wherein the ancillary data is grey scale data.

Claim 29

The apparatus of claim 23, wherein the ancillary data in the ancillary memory is color data.