Contour detecting filter

Claim 2

A contour detecting filter (8, 10, 11) for detecting contour signals from composite video signals having luminance signals and chrominance signals frequency-multiplexed and including chrominance subcarriers by inputting series of sampling values obtained by sampling said composite video signals in the direction of horizontal scanning lines and the vertical direction in a time-series manner which are to be arranged in the form of a lattice, said contour detecting filter comprising: a detector (80-1˜80-4, 100-1˜100-4, 110-1˜110-3) for sequentially inputting one sampling value at a time from said series of sampling values to process the same as a noted sampling value thereby to detect four sampling values positioned in a point-symmetrical manner around said noted sampling value and which have the same-phased chrominance subcarriers; and an arithmetic unit (81, 82, 101-2, 102-2, 103-2, 105; 101-1 102-1, 103-1, 111-2, 111-1, 112-1, 113) for receiving said noted sampling value and said four sampling values obtained from said detector to perform arithmetic on second order differentiations of said sampling values in said direction of said horizontal scanning lines and said vertical direction.

Claim 3

A contour detecting filter in accordance with claim 1, wherein said composite video signals are sampled at a frequency equal to an integer multiple of said chrominance subcarriers.

Claim 4

A contour detecting filter in accordance with claim 2, wherein sampling values aligned in said vertical direction include alternately antiphased chrominance subcarriers.

Claim 5

A contour detectng filter in accordance with claim 1, further including a multiplier (83, 108, 117) for multiplying the output of said arithmetic unit by a predetermined real number thereby to perform contour correction.

Claim 6

A contour detecting filter in accordance with claim 2, wherein, assuming that a sampling point in the horizontal scanning direction is indicated by i, a line number of horizontal scanning is indicated by j and a sampling value positioned on a lattice point (i, j) is indicated by S(i, j), said detector detects (80-1˜80-4, 100-1˜100-4, 110-1˜110-3) four sampling values S(i-2, j-1), S(i+2, j-1), S(i-2, j+1) and S(i+2, j+1) with reference to said noted sampling value S(i, j).

Claim 7

A contour detecting filter in accordance with claim 5, wherein said detector comprises a first delay circuit (80-1, 100-1) for delaying its input sampling value by a period (4T) four times a sampling period T, a second delay circuit (80-2, 100-2) for delaying the output from said first delay circuit by a period (H-2T) obtained by subtracting a period (2T) twice said sampling period T from one horizontal scanning interval H, a third delay circuit (80-3, 100-3) for delaying the output from said second delay circuit by said period (H-2T) and a fourth delay circuit (80-4, 100-4) for delaying the output from said third delay circuit by said period (4T), said input in said first delay circuit being S(i-2, j-1), said output from said first delay circuit being S(i+2, j-1), said output from said second delay circuit being S(i, j), said output from said third delay circuit being S(i-2, j+1) and said output from said fourth delay circuit being S(i+2, j+1).

Claim 8

A contour detecting filter in accordance with claim 6, wherein said arithmetic unit (81, 82, 101-1, 102-1, 103-1, 101-2, 102-2, 103-2) performs arithmetic on S(i-2, j-1)+S(i+2, j-1)+S(i-2, j+1)+S(i+2, j+1)-4·S(i, j) to output the result.

Claim 9

A contour detecting filter in accordance with claim 7, wherein said arithmetic unit (81, 82) comprises an adder (82) for adding up a value obtained by multiplying said output from said second delay circuit by -4, said input and output of said first delay circuit and said outputs of said third and fourth delay circuits to output the result.

Claim 10

A contour detecting filter in accordance with claim 6, wherein said arithmetic unit (101-1˜103-1, 101-2˜103-1, 106) performs arithmetic on 1/2 S(i, j)-1/4{S(i-2, j-1)+S(i+2, j+1)} when an absolute value |S(i-2, j-1)-S(i+2, j+1) is greater than an absolute value |S(i+2, j-1)-S(i-2, j+1)| while performing arithmetic on 1/2·S(i, j)-1/4·{S(i+2, j-1)+S(i-2, j+1)} when said absolute value |S(i-2, j-1)-S(i+2, j+1)| is less than or equal to said absolute value |S(i+2, j-1)-S(i-2, j+1).

Claim 11

A contour detecting filter in accordance with claim 9, wherein said arithmetic unit comprises: a first operation circuit (101-1, 102-1, 103-1, 105) for subtracting a value obtained by adding up said outputs of said first and fourth delay circuits (100-1, 100-4) and multiplying the result by 1/4 from a value obtained by multiplying said output of said second delay circuit by 1/2, a second operation circuit (101-2, 102-2, 103-2, 105) for subtracting a value obtained by adding up said outputs of said first and third delay circuits and multiplying the result by 1/4 from a value obtained by multiplying said output of said second delay circuit by 1/2, a third operation circuit (103-3, 104-1) for performing subtraction on said input of said first delay circuit and said output of said fourth delay circuit to obtain the absolute value thereof, a fourth operation circuit (103-4, 104-2) for performing subtraction on said outputs of said first and third delay circuits to obtain the absolute value thereof, and an output circuit (106, 107) for selecting the output of said first operation circuit when the output of said third operation circuit is greater than that of said fourth operation circuit while selecting the output of said second operation circuit when said output of said fourth operation circuit is greater than said output of said third operation circuit.

Claim 12

A contour detecting filter in accordance with claim 2, wherein said chrominance subcarriers included in said four sampling values obtained from said detector are antiphased to said chrominance subcarrier included in said noted sampling value.

Claim 13

A contour detecting filter in accordance with claim 11, wherein, assuming that a sampling point in the direction of horizontal scanning is indicated by i, a line number of horizontal scanning is indicated by j and a sampling value positioned on a lattice point (i, j) is indicated by S(i, j), said detector detects four sampling values S(i, j-1), S(i-2, j), S(i+2, j) and S(i, j+1) with respect to said noted sampling value S(i, j).

Claim 14

A contour detecting filter in accordance with claim 12, wherein said detector comprises a first delay circuit (110-1) for delaying its input sampling value by a period (H-2T) obtained by subtracting a period (2T) twice the sampling period T from one horizontal scanning interval H, a second delay circuit (110-2) for delaying the output of said first delay circuit by a period (4T) four times the sampling period T and a third delay circuit (110-3) for delaying the output of said second delay circuit by said period (H-2T), said input in said first delay circuit being S(i, j-1), said output of said delay circuit being S(i-2, j), said output of said second delay circuit being S(i+2, j) and said output of said third delay circuit being S(i, j+1).

Claim 15

A contour detecting filter in accordance with claim 13, wherein said arithmetic unit performs arithmetic on 1/4·{S(i-2, j)+S(i+2, j)-S(i, j-1)-S(i, j+1)} when an absolute value |S(i, j-1)-S(i, j+1)| is greater than an absolute value |S(i-2, j)-S(i+2, j)| while performing arithmetic on -1/4·{S(i-2, j)+S(i+2, j)-S(i, j-1)-S(i, j+1)} when said absolute value |S(i, j-1)-S(i, j+1)| is less than or equal to said absolute value |S(i-2, j)-S(i+2, j)|.

Claim 16

A contour detecting filter in accordance with claim 14, wherein said arithmetic unit comprises: a first operation circuit (112-3, 114-1) for performing subtraction on said input of said first delay circuit (110-1) and said output of said third delay circuit (110-3) to operate the absolute value, a second operation circuit (111-2, 114-2) for performing subtraction on said outputs of said first and second (110-2) delay circuits to operate the absolute value, a third operation circuit (111-1, 111-2, 112-1) for subtracting a value obtained by adding up said input of said first delay circuit and said output of said third delay circuit from a value obtained by adding up said outputs of said first and second delay circuits, and an output circuit (115, 116) for selecting said output of said third operation circuit when said output of said first operation circuit is greater than said output of said second operation circuit while inverting and selecting said output of said third circuit when said output of said second operation circuit is greater than said output of said first operation circuit.

Claim 17

A contour detecting filter for detecting contour signals from composite video signals having luminance signals and chrominance signals frequency-multiplexed and including chrominance subcarriers by inputting series of sampling values obtained by sampling said composite video signals in a series manner in the direction of horizontal scanning lines thereof and the vertical direction to be arranged in the form of a lattice, said contour detecting filter comprising: a line memory (13) sequentially detecting three sampling values having a period of one horizontal scanning interval from said series of sampling values; a vertical low-pass filter (14) receiving said three sampling values obtained from said line memory for detecting low-frequency components in said vertical direction; a horizontal high-pass filter (15) cascade-connected to said vertical low-pass filter for detecting high frequency components in said direction of said horizontal scanning lines; a vertical high-pass filter (16) receiving said three sampling values obtained from said line memory for detecting high frequency components in said vertical direction; a horizontal low-pass filter (17) cascade-connected to said vertical high-pass filter for detecting low frequency components in said direction of horizontal scanning lines; a change detecting circuit (18) receiving said three sampling values obtained from said line memory for performing arithmetic on the amounts of changes of said sampling values in said direction of horizontal scanning lines and said vertical direction thereby to detect the direction having the larger amount of sampling value changes; and an output circuit (19) for selecting the output of said horizontal high-pass filter when said change detecting circuit indicates said direction of horizontal scanning lines while selecting the output of said horizontal low-pass filter when said change detecting circuit indicates said vertical direction.

Claim 18

A contour detecting filter for detecting contour signals from composite video signals having luminance signals and chrominance signals frequency-multiplexed and including chrominance subcarriers by inputting series of sampling values obtained by sampling said composite video signals in a series manner in the direction of horizontal scanning lines thereof and the vertical direction to be arranged in the form of a lattice, said contour detecting filter comprising: a line memory (13) sequentially detecting three sampling values having a period of one horizontal scanning interval from said series of sampling values; a vertical low-pass filter (14) receiving said three sampling values obtained from said line memory for detecting low-frequency components in said vertical direction; a horizontal high-pass filter (15) cascade-connected to said vertical low-pass filter for detecting high frequency components in said direction of said horizontal scanning lines; a vertical high-pass filter (16) receiving said three sampling values obtained from said line memory for detecting high frequency components in said vertical direction; a horizontal low-pass filter (17) cascade-connected to said vertical high-pass filter for detecting low frequency components in said direction of horizontal scanning lines; a change detecting circuit (18) receiving said three sampling values obtained from said line memory for performing arithmetic on the amounts of changes of said sampling values in said direction of horizontal scanning lines and said vertical direction thereby to detect the direction having the larger amount of sampling value changes; and an output circuit (19) for selecting the output of said horizontal high-pass filter when said change detecting circuit indicates said direction of horizontal scanning lines while selecting the output of said horizontal low-pass filter when said change detecting circuit indicates said vertical direction.

Claim 19

A contour detecting filter in accordance with claim 16, wherein sampling values aligned in said vertical direction include chrominance subcarriers alternately antiphased to each other.

Claim 20

A contour detecting filter in accordance with claim 17, wherein said composite video signals are sampled at a frequency equal to 4 times that of the chrominance subcarriers.

Claim 21

A contour detecting filter in accordance with claim 18, wherein said line memory comprises a first delay circuit (130-1) for delaying input sampling values by one horizontal scanning interval (H) and a second delay circuit (130-2) for delaying the output of said first delay circuit by said period (H), to detect the input and the output of said first delay circuit and the output of said second circuit as three sampling values respectively having said period of said one horizontal scanning interval.

Claim 22

A contour detecting filter in accordance with claim 19, wherein said vertical low-pass filter (14) comprises a first adder (141) for adding up a value obtained by multiplying said input of said first delay circuit by (130-1) 1/4, a value obtained by multiplying said output of said first delay circuit (130-1) by 1/2 and a value obtained by multiplying said output of said second delay circuit (130-2) by 1/4 to output the result.

Claim 23

A contour detecting filter in accordance with claim 20, wherein said horizontal high-pass filter (15) comprises a third delay circuit (150-1) for delaying the output of said vertical low-pass filter by a period (2T) twice said sampling period T, a fourth delay circuit (150-2) for delaying the output of said third delay circuit by said period (2T) and a second adder (153) for adding up a value obtained by multiplying said input of said third delay circuit by -1/4, a value obtained by multiplying said output of said third delay circuit by 1/2 and a value obtained by multiplying the output of said fourth delay circuit by -1/4 to output the result.

Claim 24

A contour detecting filter in accordance with claim 19, wherein said vertical high-pass filter (16) comprises a third adder (161) for adding up a value obtained by multiplying the input of said first delay circuit (130-1) by -1/4, a value obtained by multiplying the output of said first delay circuit by 1/2 and a value obtained by multiplying the output of said second delay circuit (130-2) by -1/4.

Claim 25

A contour detecting filter in accordance with claim 22, wherein said horizontal low-pass filter (17) comprises a fifth delay circuit (170-1) for delaying the output of said vertical high-pass filter (16) by a period (2T) twice the sampling period T, a sixth delay circuit (170-2) for delaying the output of said fifth delay circuit by said period (2T) and a fourth adder (172) for adding up a value obtained by multiplying the input of said fifth delay circuit by 1/4, a value obtained by multiplying the output of said fifth delay circuit by 1/2 and a value obtained by multiplying the output of said sixth delay circuit by 1/4 to output the result.

Claim 26

A contour detecting filter in accordance with claim 19, wherein said change detecting circuit (18) comprises a seventh delay circuit (180-1) for delaying the output of said first delay circuit by a period (4T) four times the sampling period T, an eighth delay circuit (180-3) for delaying the input of said first delay circuit by a period (2T) twice the sampling period T, a ninth delay circuit for delaying the output of said second delay circuit by said period (2T) and a comparator (183) for comparing the absolute value of difference between the input and the output of said seventh delay circuit with the absolute value of difference between the outputs of said eighth and ninth delay circuits.