Method and apparatus for calibrating an adjustable frequency generator

Claim 3

The method recited in claim 1, wherein the output of the digital-to-analog converter is coupled via an adding circuit to the input of the voltage-controlled oscillator and further comprising the steps of monitoring the output voltage of the lowpass filter for the value zero, and when the value zero is reached, generating a store command for the respective digital reference value signal and the digital value corresponding to the control voltage.

Claim 4

The method recited in claim 1, wherein the output of the digital-to-analog converter is coupled via an adding circuit to the input of the voltage-controlled oscillator, and the phase detector provides two output signals, and further comprising the steps of examining the two output signals for phase equality, and, in the event of phase equality, generating a store command for the digital reference value signal and the digital value corresponding to the control voltage.

Claim 5

The method recited in claim 1, wherein the output of the digital-to-analog converter is coupled to an unoccupied contact of a switch, the switch having a further occupied contact which couples the voltage-controlled oscillator to the lowpass filter and further comprising the steps of comparing in the steady-state condition the output voltage of the digital-to-analog converter with the output voltage of the lowpass filter and, in the event of phase equality of said output voltage of the digital-to-analog converter and the output voltage of said lowpass filter, generating a store command for the digital reference value signal and the digital value corresponding to the control voltage.

Claim 6

A circuit arrangement for calibrating an adjustable frequency generator having a voltage-controlled oscillator coupled to a computer via a digital-to-analog converter, the oscillator further being coupled to a calibrating device comprising a digital phase detector and a lowpass filter forming a phase-locked loop circuit arrangement, an output of the oscillator being coupled to one input of the phase detector, and a further input of the phase detector being coupled to an adjustable frequency reference value setter of the calibrating device, said setter comprising means for supplying digital reference value signals corresponding to different frequency reference value signals to the computer and to the further input of the phase detector, said digital-to-analog converter comprising means under control of the computer for delivering a control voltage at its output to an input of the oscillator after a steady state of the phase-locked loop circuit arrangement is reached for the respective frequency reference value signal, said control voltage corresponding to an output voltage of the lowpass filter prior to the beginning of the calibrating process, means for storing a digital value corresponding to the control voltage associated with the respective digital reference value signal in the computer, and means for disconnecting the input of the oscillator from the calibrating device, the output of the digital-to-analog converter being coupled via an adding circuit to the input of the voltage-controlled oscillator and further comprising means for monitoring the output voltage of the lowpass filter for a zero value, and, when the zero value is reached, for generating a store command for the respective digital reference value signal and the digital value corresponding to the control voltage, the frequency reference value setter being connected to an address bus and a data bus of the computer and to the further input of the phase detector, said voltage monitoring circuit of the calibrating device having an input coupled to the output of the lowpass filter, and an output coupled to the address bus and the data bus of the computer, the digital-to-analog converter having an input coupled to the address bus and to the data bus of the computer and an output coupled to the adding circuit.

Claim 7

A circuit arrangement for calibrating an adjustable frequency generator having a voltage-controlled oscillator coupled to a computer via a digital-to-analog converter, the oscillator further being coupled to a calibrating device comprising a digital phase detector and a lowpass filter forming a phase-locked loop circuit arrangement, an output of the oscillator being coupled to one input of the phase detector, and a further input of the phase detector being coupled to an adjustable frequency reference value setter of the calibrating device, said setter comprising means for supplying digital reference value signals corresponding to different frequency reference value signals to the computer and to the further input of the phase detector, said digital-to-analog converter comprising means under control of the computer for delivering a control voltage at its output to an input of the oscillator after a steady state of the phase-locked loop circuit arrangement is reached for the respective frequency reference value signal, said control voltage corresponding to an output voltage of the lowpass filter prior to the beginning of the calibrating process, means for storing a digital value corresponding to the control voltage associated with the respective digital reference value signal in the computer, and means for disconnecting the input of the oscillator from the calibrating device, the output of the digital-to-analog converter being coupled via an adding circuit to the input of the voltage-controlled oscillator and further comprising means for monitoring the output voltage of the lowpass filter for a zero value, and, when the zero value is reached, for generating a store command for the respective digital reference value signal and the digital value corresponding to the control voltage, the frequency reference value setter being connected to an address bus and a data bus of the computer and to the further input of the phase detector, said voltage monitoring circuit of the calibrating device having an input coupled to the output of the lowpass filter, and an output coupled to the address bus and the data bus of the computer, the digital-to-analog converter having an input coupled to the address bus and to the data bus of the computer and an output coupled to the adding circuit.

Claim 8

A circuit arrangement for calibrating an adjustable frequency generator having a voltage-controlled oscillator coupled to a computer via a digital-to-analog converter, the oscillator further being coupled to a calibrating device comprising a digital phase detector and a lowpass filter forming a phase-locked loop circuit arrangement, an output of the oscillator being coupled to one input of the phase detector, and a further input of the phase detector being coupled to an adjustable frequency reference value setter of the calibrating device, said setter comprising means for supplying digital reference value signals corresponding to different frequency reference value signals to the computer and to the further input of the phase detector, said digital-to-analog converter comprising means under control of the computer for delivering a control voltage at its output to an input of the oscillator after a steady state of the phase-locked loop circuit arrangement is reached for the respective frequency reference value signal, said control voltage corresponding to an output voltage of the lowpass filter prior to the beginning of the calibrating process, means for storing a digital value corresponding to the control voltage associated with the respective digital reference value signal in the computer, and means for disconnecting the input of the oscillator from the calibrating device, the output of the digital-to-anlog converter being coupled via an adding circuit to the input of the voltage controlled oscillator, said phase detector having two outputs, and means for examining the two outputs for phase equality, and for generating, in the event of phase equality, a store command for the digital reference value signal and the digital value corresponding to the control voltage, the frequency reference value setter being coupled to an address bus and a data bus of the computer and to the further input of the phase detector, the two outputs of the phase detector being coupIed to inputs of a digital pulse monitoring means of the calibrating device, said monitoring means having an output coupled to the address bus and the data bus, the digital-to-analog converter having an input coupled to the address bus and the data bus of the computer and an output coupled to the adding circuit.

Claim 9

A circuit arrangement for calibrating an adjustable frequency generator having a voltage-controlled oscillator coupled to a computer via a digital-to-analog converter, the oscillator further being coupled to a calibrating device comprising a digital phase detector and a lowpass filter forming a phase-locked loop circuit arrangement, an output of the oscillator being coupled to one input of the phase detector, and a further input of the phase detector being coupled to an adjustable frequency reference value setter of the calibrating device, said setter comprising means for supplying digital reference value signals corresponding to different frequency reference value signals to the computer and to the further input of the phase detector, said digital-to-analog converter comprising means under control of the computer for delivering a control voltage at its output to an input of the oscillator after a steady state of the phase-locked loop circuit arrangement is reached for the respective frequency reference value signal, said control voltage corresponding to an output voltage of the lowpass filter prior to the beginning of the calibrating process, means for storing a digital value corresponding to the control voltage associated with the respective digital reference value signal in the computer, and means for disconnecting the input of the oscillator from the calibrating device, the output of the digital-to-anlog converter being coupled via an adding circuit to the input of the voltage controlled oscillator, said phase detector having two outputs, and means for examining the two outputs for phase equality, and for generating, in the event of phase equality, a store command for the digital reference value signal and the digital value corresponding to the control voltage, the frequency reference value setter being coupled to an address bus and a data bus of the computer and to the further input of the phase detector, the two outputs of the phase detector being coupIed to inputs of a digital pulse monitoring means of the calibrating device, said monitoring means having an output coupled to the address bus and the data bus, the digital-to-analog converter having an input coupled to the address bus and the data bus of the computer and an output coupled to the adding circuit.

Claim 10

The circuit arrangement recited in claim 5 wherein said means for disconnecting comprises a switch and the adding circuit is coupled via the switch to the output of the lowpass filter.

Claim 11

The circuit arrangement recited in claim 6 wherein said means for disconnecting comprises a switch and the adding circuit is coupled via the switch to the output of the lowpass filter.

Claim 12

A circuit arrangement for calibrating an adjustable frequency generator having a voltage-controlled oscillator coupled to a computer via a digital-to-analog converter, the oscillator further being coupled to a calibrating device comprising a digital phase detector and a lowpass filter forming a phase-locked loop circuit arrangement, an output of the oscillator being coupled to one input of the phase detector, and a further input of the phase detector being coupled to an adjustable frequency reference value setter of the calibrating device, said setter comprising means for supplying digital reference value signals corresponding to different frequency reference value signals to the computer and to the further input of the phase detector, said digital-to-analog converter comprising means under control of the computer for delivering a control voltage at its output to an input of the oscillator after a steady state of the phase-locked loop circuit arrangement is reached for the respective frequency reference value signal, said control voltage corresponding to the output voltage of the lowpass filter prior to the beginning of the calibrating process, means for storing a digital value corresponding to the control voltage associated with the respective digital reference value signal in the computer, and means for disconnecting the input of the oscillator from the calibrating device, the output of the digital-to-analog converter being coupled to an unoccupied contact of a switch, the switch having a further occupied contact which couples the voltage-controlled oscillator to the lowpass filter and further comprising means for comparing in the steady-state condition the output voltage of the digital-to-analog converter with the output voltage of the lowpass filter and, in the event of equality of said output signals, for generating a store command for the digital reference value signal and the digital value corresponding to the control voltage, the frequency reference value setter being coupled to an address bus and a data bus of the computer and to the further input of the phase detector, the digital-to-analog converter having an input coupled to the address bus and the data bus of the computer and an output coupled via the switch to an input of the oscillator, said means for comparing having an input coupled to an output of the digital-to-analog converter and an input coupled to an output of the lowpass filter and an output coupled to the address bus and data bus of the computer.

Claim 13

A circuit arrangement for calibrating an adjustable frequency generator having a voltage-controlled oscillator coupled to a computer via a digital-to-analog converter, the oscillator further being coupled to a calibrating device comprising a digital phase detector and a lowpass filter forming a phase-locked loop circuit arrangement, an output of the oscillator being coupled to one input of the phase detector, and a further input of the phase detector being coupled to an adjustable frequency reference value setter of the calibrating device, said setter comprising means for supplying digital reference value signals corresponding to different frequency reference value signals to the computer and to the further input of the phase detector, said digital-to-analog converter comprising means under control of the computer for delivering a control voltage at its output to an input of the oscillator after a steady state of the phase-locked loop circuit arrangement is reached for the respective frequency reference value signal, said control voltage corresponding to the output voltage of the lowpass filter prior to the beginning of the calibrating process, means for storing a digital value corresponding to the control voltage associated with the respective digital reference value signal in the computer, and means for disconnecting the input of the oscillator from the calibrating device, the output of the digital-to-analog converter being coupled to an unoccupied contact of a switch, the switch having a further occupied contact which couples the voltage-controlled oscillator to the lowpass filter and further comprising means for comparing in the steady-state condition the output voltage of the digital-to-analog converter with the output voltage of the lowpass filter and, in the event of equality of said output signals, for generating a store command for the digital reference value signal and the digital value corresponding to the control voltage, the frequency reference value setter being coupled to an address bus and a data bus of the computer and to the further input of the phase detector, the digital-to-analog converter having an input coupled to the address bus and the data bus of the computer and an output coupled via the switch to an input of the oscillator, said means for comparing having an input coupled to an output of the digital-to-analog converter and an input coupled to an output of the lowpass filter and an output coupled to the address bus and data bus of the computer.

Claim 14

The circuit arrangement recited in claim 9, wherein said means for disconnecting comprises a switch and the oscillator is coupled via the switch to the output of the lowpass filter.