Conditional-carry adder for multibit digital computer

Claim 2

In a multibit digital computer wherein blocks of adders, each containing at least a pair of single bit adders, are connected in parallel to add two multibit digital numbers and to respond to a C IN signal, the improvement comprising: (a) a pair of carry generating circuitry having identical elements disposed between successive single bit adders, the first one of such circuitry having a C IN signal at a logic one level applied thereto and the second one of such circuitry having a C IN signal at a logic zero level applied thereto, both such circuitries being responsive to the complement of the bits applied to the preceding single bit adder to produce a carry-in signal for the next following single bit adder; and (b) means, responsive to the C IN signal to the single bit adder operating on the least significant bits of the multibit digital numbers, for selecting the proper one of the carry-in signal out of each pair of first and second carry generating circuitries.

Claim 3

The improvement as in claim 1 wherein the pairs of carry generating circuitry between the single bit adder for the least significant bits, A1, B1, in the multibit adder and the second least significant bit operate according to the following truth table where C is the logic level of the signal out of each such circuitry: ______________________________________ C.sub.IN A1 B1 C ______________________________________ 1 0 0 0 1 1 0 1 1 0 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 0 1 0 0 1 1 1 ______________________________________

Claim 4

The improvement as in claim 2 having, additionally, at least a second pair of single bit adders wherein each one of the pairs of carry generating circuitry between the adders for the second least significant bit and the third least significant bit operates in accordance with the following truth table: ______________________________________ C.sub.IN A2 B2 C ______________________________________ 0 0 0 1 1 1 0 1 1 0 1 1 1 1 1 0 0 0 0 1 0 1 0 0 0 0 1 0 1 1 1 0 ______________________________________

Claim 5

The improvement as in claim 3 wherein each one of the carry generating circuitry between the adders for the third and fourth least significant bit operate in accordance with the truth table in claim 2.

Claim 6

The improvement as in claim 4 having, additionally, a third pair of single bit adders, wherein each one of the pairs of carry generating circuitry between the adders for the fourth and fifth least significant bits operate in accordance with the truth table in claim 3.