Circuit for controlling the load current level in a transistor

Claim 2

The combination comprising: first and second terminals for the application therebetween of an operating potential; a power transistor having a base, an emitter and a collector; means for connecting a load between the collector of said power transistor and said first power terminal; a resistive element having an impedance which is significantly less than the impedance of said load; means connecting one end of said resistive element to the emitter of said power transistor at a first node, and means connecting the other end of said resistive element to said second power terminal; means for measuring the load current through said resistive element and for controlling the conductivity fo said power transistor as a function of the current level through said resistive element including: first and second comparator transistors, each comparator transistor having a base, an emitter and a collector; means connecting the emitter of said first comparator transistor to said first node and the emitter of said second comparator transistor to said second power terminal; means for applying the same relatively constant biasing potential to the bases of said first and second comparator transistors for maintaining the collector-to-emitter current through said second comparator transistor relatively constant and for enabling the current through said first comparator transistor to vary as a function of the total current through said resistive element; and means coupled to the collectors of said first and second comparator transistors for comparing their collector currents and including means responsive to the difference between their collector currents for producing a signal coupled to the base of said power transistor for controlling its conductivity.

Claim 3

The combination comprising: first and second power terminals for the application therebetween of an operating potential; a relatively low impedance element connected betwee one of said first and second power terminal and an intermediate node; an output terminal for the connection thereto of a selectively enabled controllable switch means connec between said intermediate node and said output terminal; and means for limiting the current flowing through combination of said low impedance element and said switch means comprisin0: (a) first and second transistors, each having a base, an emitter, and a collector; and the physical sizes of said first and second transistor being ratioed such that the collector current of said first transistor is N e collector current of said second transistor for like base-to-emitter bias conditions; (b) means connecting the emitter of said second to said one of said first and second power (c) means connecting the emitter of said first transistor to said intermediate node for decreasing the base-to-emitter voltage of said first transistor in response to increasing values of current through said low impedance element and said switch means; (d) means for applying the same potential to the bases said first and second transistors; (e) a summing node; (f) means, coupled between the collectors of said first and second transistors and said summing node, for comparing the collector currents in said first and second transistors and for producing a first valued slgnal at said summing node when the difference between the collector currents is of one polarity and a second valued signal when the difference between the collector currents is of opposite polarity to said one polarity; and means coupled between said summing node and said controllable switch means for limiting the current through said switch means, in response to the presence of said second valued signal.

Claim 4

The combination comprising: first and second power terminals for the application therebetween of an operating potential; a relatively low impedance element connected betwee one of said first and second power terminal and an intermediate node; an output terminal for the connection thereto of a selectively enabled controllable switch means connec between said intermediate node and said output terminal; and means for limiting the current flowing through combination of said low impedance element and said switch means comprisin0: (a) first and second transistors, each having a base, an emitter, and a collector; and the physical sizes of said first and second transistor being ratioed such that the collector current of said first transistor is N e collector current of said second transistor for like base-to-emitter bias conditions; (b) means connecting the emitter of said second to said one of said first and second power (c) means connecting the emitter of said first transistor to said intermediate node for decreasing the base-to-emitter voltage of said first transistor in response to increasing values of current through said low impedance element and said switch means; (d) means for applying the same potential to the bases said first and second transistors; (e) a summing node; (f) means, coupled between the collectors of said first and second transistors and said summing node, for comparing the collector currents in said first and second transistors and for producing a first valued slgnal at said summing node when the difference between the collector currents is of one polarity and a second valued signal when the difference between the collector currents is of opposite polarity to said one polarity; and means coupled between said summing node and said controllable switch means for limiting the current through said switch means, in response to the presence of said second valued signal.

Claim 5

The combination as claimed in claim 2, wherein said controllable switch means is a power transistor having a base, an emitter and a collector; wherein the emitter of said power transistor is connected to one end of said relatively low impedance element; wherein the collector of said power transistor is connect to the said output terminal; and said means coupled between said summing node and said controllable switch means includes means coupled to the base of said power transistor.

Claim 6

The combination as claimed in claim 3 wherein the impedance of said relatively low impedance element is a small percentage of the impedance of said load.