Clock control circuit for phase control

Claim 2

A clock control circuit for use in situations where it is desired to generate stable timing signals keyed to the phase angle of a plurality of input reference frequency locked signals, said circuit comprising, means for receiving and selecting between said plurality of input signals, means for comparing the phase of a selected input signal with the phase of an internally generated signal, means controlled by mismatches between said phase comparison for adjusting said internally generated signal until said mismatches disappear, means, including said last-mentioned means, for generating said timing control signals from said selected input signal, means controlled by said selecting means and the selection of a new input signal for modifying the phase angle of said internally generated signal to equal the phase angle of said new input signal without modifying said timing signals.

Claim 3

The invention set forth in claim 1 wherein said adjusting means includes a feedback loop and wherein said modifying means includes means for changing the phase angle of signals on said feedback loop.

Claim 4

The invention set forth in claim 2 wherein said adjusting means includes a counter having an input for accepting a feedback control signal and wherein an output of said counter is said internally generated signal, said counter having means jointly responsive to said selecting means and to said newly selected input signal for immediately resetting the count of said counter thereby forcing said internally generated signal to be in phase with said new input signal.

Claim 5

The invention set forth in claim 3 wherein said adjusting means includes voltage controlled oscillator means responsive to the output of said comparing means for providing said feedback control signal to said counter.

Claim 6

The invention set forth in claim 4 wherein said adjusting means includes a signal divider circuit for producing said control signals as well as framing control signals.

Claim 7

The invention set forth in claim 1 wherein said adjusting means includes a counter having an input for receiving a feedback control signal and wherein said output of said counter is said internally generated signal, said counter having means jointly responsive to a clock changing signal and to said timing control signal for immediately resetting the count of said timer thereby forcing said internally generated signal to be in phase with said timing control signal.

Claim 8

A control circuit for use in a PBX system for controlling the timing of data on a data bus such that said data is in phase synchronization with reference signals received from said other PBX systems, said control circuit comprising means for selecting a first one of said reference signals, means for generating a data bus timing signal having a phase identical with said selected first reference signal, means, including a feedback signal having a phase related to said phase of said generated data bus timing signal, for locking said phase of said generated data bus timing signal to the phase of said selected first reference signal, means for selecting a second one of said reference signals while said bus timing signal is locked to said first selected reference signal, means for changing said locking of said bus timing signal from said first reference signal to said selected second signal, said changing means including means for momentarily forcing said phase of said feedback signal to be identical with the phase of said selected second signal so that said phase of said bus timing signal does not change at the instant of said changeover.

Claim 9

A control circuit for use in a PBX system for controlling the timing of data on a data bus such that said data is in phase synchronization with reference signals received from said other PBX systems, said control circuit comprising means for selecting a first one of said reference signals, means for generating a data bus timing signal having a phase identical with said selected first reference signal, means, including a feedback signal having a phase related to said phase of said generated data bus timing signal, for locking said phase of said generated data bus timing signal to the phase of said selected first reference signal, means for selecting a second one of said reference signals while said bus timing signal is locked to said first selected reference signal, means for changing said locking of said bus timing signal from said first reference signal to said selected second signal, said changing means including means for momentarily forcing said phase of said feedback signal to be identical with the phase of said selected second signal so that said phase of said bus timing signal does not change at the instant of said changeover.

Claim 10

The invention set forth in claim 7 wherein said feedback circuit includes a resettable counter operable under joint control of said changing means and said selected second reference signal.

Claim 11

The invention set forth in claim 8 wherein said locking means further includes means for producing an output control signal when the phase between said selected reference signal and said feedback signal is different.

Claim 12

The invention set forth in claim 7 wherein said control circuit further includes means for monitoring the phase and frequency difference between said selected reference signal and said timing control signal, means for selecting a new input reference signal in response to a detected phase or frequency change of a certain magnitude.

Claim 13

The invention set forth in claim 9 wherein said PBX has a second control circuit and wherein one of said control circuits operates in the primary mode and the other of said control circuits operates in the backup mode, each said circuit including means for selecting one of said control circuits as said backup circuit, means for forcing said phase of said feedback signal of said selected back-up circuit to be identical with said phase of said timing control signal of said control circuit which has not been so selected.