US4670745A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Video display address generator
Assignee: Motorola Solutions Inc
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Filing: 1983-11-15
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Granted: 1987-06-02
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Expires: 2003-11-15
Abstract
Abstract A video raster display system having a dedicated display address generator is provided. In addition to a microprocessor contained within the video display system providing addresses to a memory the display address generator also generates addresses. The display address generator has a logic unit having a first and a second bus as inputs. A first plurality of registers, some of which are controllably coupled to said first bus and some of which are controllably coupled to said second bus, receives inputs from the microprocessor. A second plurality of registers, some of which are controllably coupled to said first bus and some of which are controllably coupled to said second bus, receives inputs from a video data generator. A third plurality of registers, some of which are controllably coupled to said first bus and some of which are controllably coupled to said second bus, receives the output from the logic unit to controllably provide this output to the logic unit for subsequent operations.
Inventors
- 👤 Patrick J. O'Malley
- 👤 William M. Peterson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 18:09
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G09; G09G; G09G5/00; G09G5/18; G06F3/00; G06F3/14; G06F3/153
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
184 words
A raster display address generator comprising: an arithmetic and logic unit for generating raster display addresses at an output; a first and a second bus each coupled to the arithmetic and logic unit; a first set of registers coupled to the first bus for receiving at least base address, vertical size and horizontal size inputs from a microprocessor; at least one register coupled to the first bus for receiving inputs from a memory; at least one register coupled to the first bus for receiving and storing the output from the arithmetic and logic unit; at least one register coupled to the second bus for receiving start inputs from the microprocessor; at least one register coupled to the first bus for receiving character code inputs from a video data generator; at least one register coupled to the second bus for receiving a video timing input; at least one register coupled to the second bus for receiving inputs from the video data generator; and a second set of registers coupled to the second bus for receiving inputs from the output of the arithmetic and logic unit.
Claim 2
Dependent Claim
184 words
A raster display address generator comprising: an arithmetic and logic unit for generating raster display addresses at an output; a first and a second bus each coupled to the arithmetic and logic unit; a first set of registers coupled to the first bus for receiving at least base address, vertical size and horizontal size inputs from a microprocessor; at least one register coupled to the first bus for receiving inputs from a memory; at least one register coupled to the first bus for receiving and storing the output from the arithmetic and logic unit; at least one register coupled to the second bus for receiving start inputs from the microprocessor; at least one register coupled to the first bus for receiving character code inputs from a video data generator; at least one register coupled to the second bus for receiving a video timing input; at least one register coupled to the second bus for receiving inputs from the video data generator; and a second set of registers coupled to the second bus for receiving inputs from the output of the arithmetic and logic unit.
Claim 3
Dependent Claim
70 words
The raster display address generator of claim 1 further including means for placing zeros on the second bus so that zeros can be combined with contents from one of the registers coupled to the first bus when it is desired to transfer the contents from said one of the registers coupled to the first bus, to a register that is coupled to the output of the arithmetic and logic unit.
Claim 4
Dependent Claim
62 words
The raster display address generator of claim 1 wherein the at least one register coupled to the first bus for receiving the output from the arithmetic and logic unit is used to temporarily store the output from the arithmetic and logic unit so that it can be added to contents from one of the registers coupled to said second bus if desired.
Claim 5
Dependent Claim
18 words
The raster display address generator of claim 1 wherein the arithmetic and logic unit is a full adder.
Claim 6
Dependent Claim
49 words
The raster display address generator of claim 1 wherein at least two of the registers of the first set of registers are for receiving vertical offset and horizontal offset information so that the raster display address generator can provide addresses useful in scrolling in both vertical and horizontal directions.
Claim 7
Dependent Claim
128 words
A raster display address generator for generating addresses for a video display system having a microprocessor, memory, and a video generator, comprising: first means for combining coupled to said microprocessor, said memory, and said video generator; means for providing a base address coupled to the first means; means for providing horizontal offset data coupled to the first means; means for providing vertical size data coupled to the first means; means for providing horizontal size data coupled to the first means; means for temporarily storing an output from the first means and being coupled back to the first means; means for providing current raster line location coupled to the first means; and means for providing a current address of the raster display address generator coupled to the first means.
Claim 8
Dependent Claim
128 words
A raster display address generator for generating addresses for a video display system having a microprocessor, memory, and a video generator, comprising: first means for combining coupled to said microprocessor, said memory, and said video generator; means for providing a base address coupled to the first means; means for providing horizontal offset data coupled to the first means; means for providing vertical size data coupled to the first means; means for providing horizontal size data coupled to the first means; means for temporarily storing an output from the first means and being coupled back to the first means; means for providing current raster line location coupled to the first means; and means for providing a current address of the raster display address generator coupled to the first means.
Claim 9
Dependent Claim
18 words
The raster display address generator of claim 6 wherein the first means is an arithmetic and logic unit.
Claim 10
Dependent Claim
151 words
A raster display system having a microprocessor, video timing circuit, memory, video generator, video display, and a display address generator, the display address generator comprising: a dedicated arithmetic and logic unit for generating raster display addresses; a first register for receiving a base address from the microprocessor being controllably coupled to the arithmetic and logic unit; a current line register for receiving a current raster line from the video timing circuit and being controllably coupled to the arithmetic and logic unit; a register for receiving vertical offset data from the microprocessor being controllably coupled to the arithmetic and logic unit; a register for receiving horizontal offset data from a microprocessor and being controllably coupled to the arithmetic and logic unit; and a register coupled to the output of the arithmetic and logic unit for temporarily storing the output and being controllably coupled to the input of the arithmetic and logic unit.
Claim 11
Dependent Claim
151 words
A raster display system having a microprocessor, video timing circuit, memory, video generator, video display, and a display address generator, the display address generator comprising: a dedicated arithmetic and logic unit for generating raster display addresses; a first register for receiving a base address from the microprocessor being controllably coupled to the arithmetic and logic unit; a current line register for receiving a current raster line from the video timing circuit and being controllably coupled to the arithmetic and logic unit; a register for receiving vertical offset data from the microprocessor being controllably coupled to the arithmetic and logic unit; a register for receiving horizontal offset data from a microprocessor and being controllably coupled to the arithmetic and logic unit; and a register coupled to the output of the arithmetic and logic unit for temporarily storing the output and being controllably coupled to the input of the arithmetic and logic unit.
Claim 12
Dependent Claim
50 words
The raster display system of claim 8 further including a register for receiving horizontal size data from the microprocessor and being controllably coupled to the arithmetic and logic unit; and a register for receiving vertical size data from the microprocessor and being controllably coupled to the arithmetic and logic unit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-06-01 | 1990-12-01 | 1991-06-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-06-01 | 1994-12-01 | 1995-06-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-06-01 | 1998-12-01 | 1999-06-02 | $7700.00 | Window Closed / Lapsed |