US4669057A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data collection terminal interrupt structure
Assignee: Bull HN Information Systems Inc
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Filing: 1983-10-03
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Granted: 1987-05-26
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Expires: 2003-10-03
Abstract
Abstract A data collection terminal includes a microprocessor, a memory and a number of devices coupled to a system bus. An interrupt controller processes the device interrupt requests by sending a vector address out on the system bus to enable the microprocessor to branch to a microprogram to process the interrupt request. Apparatus is provided to receive the vector address to generate an interrupt clear signal for those interrupts which are transitory in nature. Typical examples are a document being inserted in a device or a card seated in a device.
Inventors
- 👤 Vincent M. Clark, Jr.
- 👤 David R. Bourgeois
- 👤 Dennis W. Chasse
- 👤 Todd R. Comins
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 20:13
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/24; G06K; G06K17/00; G06K17/0022
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
250 words
A data collection terminal comprises: microprocessor means; a plurality of devices, each coupled to one of a plurality of interrupt request signal lines, one of said plurality of devices generating one of a plurality of interrupt request signals on said one of said plurality of interrupt request signal lines when said one of said plurality of devices requires said microprocessor means to process an interrupt; interrupt controller means coupled to said each of said plurality of interrupt-signal lines for receiving said one of said plurality of interrupt request signals and generating a microprocessor interrupt signal, said each of said plurality of interrupt signal lines being coupled to said interrupt controller means establishing a predetermined priority in accordance with a terminal of said interrupt controller means to which said each of said plurality of interrupt signal lines is coupled; said microprocessor means being coupled to said interrupt controller means for receiving said microprocessor interrupt signal and generating an interrupt acknowledge signal when said microprocessor means is ready to process the interrupt; said interrupt controller means being responsive to said interrupt acknowledge signal for generating a plurality of vector address signals, said microprocessor means being responsive to said vector address signals for branching to a microprogram to process the interrupt; and decoder means coupled to said interrupt controller means and to said microprocessor means and responsive to said plurality of vector address signals and said interrupt acknowledge signal for generating a device clear signal for predetermined devices of said plurality of devices.
Claim 2
Dependent Claim
250 words
A data collection terminal comprises: microprocessor means; a plurality of devices, each coupled to one of a plurality of interrupt request signal lines, one of said plurality of devices generating one of a plurality of interrupt request signals on said one of said plurality of interrupt request signal lines when said one of said plurality of devices requires said microprocessor means to process an interrupt; interrupt controller means coupled to said each of said plurality of interrupt-signal lines for receiving said one of said plurality of interrupt request signals and generating a microprocessor interrupt signal, said each of said plurality of interrupt signal lines being coupled to said interrupt controller means establishing a predetermined priority in accordance with a terminal of said interrupt controller means to which said each of said plurality of interrupt signal lines is coupled; said microprocessor means being coupled to said interrupt controller means for receiving said microprocessor interrupt signal and generating an interrupt acknowledge signal when said microprocessor means is ready to process the interrupt; said interrupt controller means being responsive to said interrupt acknowledge signal for generating a plurality of vector address signals, said microprocessor means being responsive to said vector address signals for branching to a microprogram to process the interrupt; and decoder means coupled to said interrupt controller means and to said microprocessor means and responsive to said plurality of vector address signals and said interrupt acknowledge signal for generating a device clear signal for predetermined devices of said plurality of devices.
Claim 3
Dependent Claim
33 words
The terminal of claim 1 wherein said predetermined devices includes a magnetic wand reader having a first priority, a badge reader having a second priority and a multifunction reader having a third priority.
Claim 4
Dependent Claim
88 words
The terminal of claim 2 wherein said interrupt controller means comprises: first slave interrupt controller means coupled to said magnetic wand reader and receiving a first of said plurality of interrupt request signals for generating a first interrupt signal when said magnetic wand reader requires said microprocessor means to process the interrupt, and coupled to said badge reader and receiving a second of said plurality of interrupt request signals for generating said first interrupt request signal when said badge reader requires said microprocessor means to process the interrupt.
Claim 5
Dependent Claim
50 words
The terminal of claim 3 wherein said interrupt controller means further comprises: second slave interrupt controller means coupled to said multifunction reader and receiving a third plurality of interrupt request signals for generating a second interrupt request signal when said multifunction reader requires said microprocessor means to process the interrupt.
Claim 6
Dependent Claim
124 words
The terminal of claim 4 wherein said interrupt controller means further comprises: master interrupt controller means coupled to said first and said second slave interrupt controller means and responsive to said first or said second interrupt request signal for generating said microprocessor interrupt signal, said master interrupt controller means being further coupled to said microprocessor means for receiving a first occurrence of said interrupt acknowledge signal from said microprocessor means in response to said microprocessor interrupt signal and generating a plurality of cascade signals for selecting said first slave interrupt controller means if said master interrupt controller means received said first interrupt request signal and selecting said second slave interrupt controller means if said master interrupt controller means received said second interrupt request signal.
Claim 7
Dependent Claim
78 words
The terminal of claim 5 wherein said first slave interrupt controller means is responsive to a second occurrence of said interrupt acknowledge signal from said microprocessor means for generating said vector address signals if said cascade signals selected said first slave interrupt controller means; said second slave interrupt controller means is responsive to said second occurrence of said interrupt acknowledge signal for generating said vector address signals if said cascade signals selected said second slave interrupt controller means.
Claim 8
Dependent Claim
92 words
The terminal of claim 6 wherein said microprocessor means comprises: a microprocessor for generating a read signal, an input/output signal, and a predetermined plurality of address signals to enable said decoder means; a first decoder responsive to said predetermined plurality of address signals for generating a first enable signal; a first negative AND gate responsive to said read signal and said input/output signal for generating a second enable signal; and a second negative AND gate responsive to said first enable signal and said second enable signal for generating a third enable signal.
Claim 9
Dependent Claim
103 words
The terminal of claim 7 wherein said decoder means comprises: a register coupled to said interrupt controller means and responsive to said second occurrence of said interrupt acknowledge signal for storing said vector address signals; a second decoder coupled to said register and said microprocessor means and responsive to said third enable signal and a first plurality of said vector address signals for generating a first plurality of device clear signals; and; a third decoder coupled to said register and said microprocessor means and responsive to said third enable signal and a third plurality for generating a second plurality of device clear signals.
Claim 10
Dependent Claim
48 words
The terminal of claim 8 wherein said magnetic wand reader generates a third interrupt request signal to said first slave interrupt controller means and receives a first device clear signal of said first plurality of device clear signals when said magnetic wand reader has completed reading a document.
Claim 11
Dependent Claim
47 words
The terminal of claim 8 wherein said badge reader generates a fourth interrupt request signal to said first slave interrupt controller means and receives a second device clear signal of said first plurality of device clear signals when a badge is fully seated in said badge reader.
Claim 12
Dependent Claim
47 words
The terminal of claim 8 wherein said multifunction reader generates a fourth interrupt request signal to said second interrupt controller means and receives in return a third device clear signal of said second plurality of device clear signals when a card is inserted in said multifunction reader.
Claim 13
Dependent Claim
51 words
The terminal of claim 8 wherein said multifunction reader generates a fifth interrupt request signal to said second interrupt controller means and receives in return a fourth device clear signal of said second plurality of device clear signals when the trailing edge of said card is detected in said multifunction reader.
Claim 14
Dependent Claim
49 words
The terminal of claim 8 wherein said multifunction reader generates a sixth interrupt request signal to said second interrupt controller means and receives in return a fifth device clear signal of said second plurality of device clear signals when said card orientation is in error in said multifunction reader.
References Cited (Backward Citations)
US4438492A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-05-25 | 1990-11-24 | 1991-05-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-05-25 | 1994-11-24 | 1995-05-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-05-25 | 1998-11-24 | 1999-05-26 | $7700.00 | Window Closed / Lapsed |