US4668989A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fading circuit for video signals
Assignee: US Philips Corp
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Filing: 1985-04-08
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Granted: 1987-05-26
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Expires: 2005-04-08
Abstract
Abstract The fading circuit comprises first and second video signal inputs (1,12) for receiving 8 bit parallel digitally encoded video signals and first and second fading control signal inputs (5,16) for receiving 8 bit parallel fading control signals. First and second multipliers (4,15) multiply the video signals by the fading control signals. The outputs of the multipliers (4,15) are truncated to 9 bits and fed to first and second inputs of an adding arrangement (11). A dither signal is fed from a dither signal generator (22) to the carry input (24) of the adding arrangement (11). The output of the adding arrangement (11) is fed to a ROM (28) which is programmed to add 1/256th of the output of the adding arrangement (11) to the output of the adding arrangement (11) and produce an 8 bit output which is applied to the output (31) of the fading circuit. By adding the dither signal amplitude transitions in the output signal at particular settings of the fading control signals are blurred and do not produce such a disturbing effect on the display screen.
Inventors
- 👤 Thomas C. Mackereth
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 04:07
CPC Classifications
H; H04; H04N; H04N7/00; H04N7/01; H04N7/0117; H04N7/0122; G; G06; G06T; G06T3/00; G06T3/40; H04N5/00; H04N5/222; H04N5/262; H04N5/2628; H04N5/265
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
187 words
A fading circuit for video signals which comprise digital samples of k binary digits where k is greater than 1 comprising: a plurality of n video signal inputs, where n is an integer, each of said inputs receiving one of said video signals; a plurality of n fading control signal outputs for receiving n fading control binary signals, each fading control signal having m bits, where m is an integer greater than 1; a multiplicity of digital multipliers, each multiplier connected to receive one of said video signals and a respective one of said fading control signals, each multiplier providing an output signal of (k+m) bits which includes (k+1) most significant bits; an adding means connected to receive at least the (k+1) most significant bits of each multiplier output signal and, producing a summation signal of k bits; means for generating a digital dither signal of one bit which varies randomly or pseudo-randomly, and adding said bit to said summation signal as the (k+1) most significant bit; and means for truncating said summation signal to a k bit digital signal which comprises the fading circuit output signal.
Claim 2
Dependent Claim
187 words
A fading circuit for video signals which comprise digital samples of k binary digits where k is greater than 1 comprising: a plurality of n video signal inputs, where n is an integer, each of said inputs receiving one of said video signals; a plurality of n fading control signal outputs for receiving n fading control binary signals, each fading control signal having m bits, where m is an integer greater than 1; a multiplicity of digital multipliers, each multiplier connected to receive one of said video signals and a respective one of said fading control signals, each multiplier providing an output signal of (k+m) bits which includes (k+1) most significant bits; an adding means connected to receive at least the (k+1) most significant bits of each multiplier output signal and, producing a summation signal of k bits; means for generating a digital dither signal of one bit which varies randomly or pseudo-randomly, and adding said bit to said summation signal as the (k+1) most significant bit; and means for truncating said summation signal to a k bit digital signal which comprises the fading circuit output signal.
Claim 3
Dependent Claim
14 words
A fading circuit as claimed in claim 1, wherein n is equal to two.
Claim 4
Dependent Claim
14 words
A fading circuit as claimed in claim 1, wherein m is equal to k.
Claim 5
Dependent Claim
16 words
A fading circuit as claimed in claim 1, characterised in that k is equal to eight.
Claim 6
Dependent Claim
31 words
A fading circuit as claimed in claim 1, wherein said adding means comprises (n-1) binary full adders arranged in cascade, the dither signal being applied to the final full adder circuit.
Claim 7
Dependent Claim
21 words
A fading circuit as claimed in claim 1, wherein said dither signal is generated by a pseudo random binary sequence generator.
Claim 8
Dependent Claim
27 words
A fading circuit as claimed in claim 1 wherein means are provided for adding 1/256th of the output of said adding means to said truncated summation signal.
Claim 9
Dependent Claim
32 words
A fading circuit as claimed in claim 1 further comprising a read-only memory connected to said adding means output for adding 1/256th of said adding means output to said truncated summation signal.
Claim 10
Dependent Claim
26 words
A fading circuit as claimed in claim 8, characterised in that the output of the read only memory is equal to its input divided by two.
Claim 11
Dependent Claim
27 words
A fading circuit as claimed in claim 8, wherein the read only memory gives an output of 255 for any input greater than or equal to 511.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-05-25 | 1990-11-24 | 1991-05-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-05-25 | 1994-11-24 | 1995-05-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-05-25 | 1998-11-24 | 1999-05-26 | $7700.00 | Window Closed / Lapsed |