Video signal processing apparatus

Claim 1

Apparatus for processing video signals in which an input digital video signal corresponding to a displayed image and occurring in successive samples derived at a sampling clock frequency is divided to form N channel signals, N being an integer large than 2, said input digital video signal including successive groups of said samples corresponding to successive unit time intervals and each said group being divided into N sections of successive samples, the samples within each section corresponding to a defined area of the displayed image, said apparatus comprising: addressable memory means receiving said successive samples for storing the same at selected write addresses and for reading out the stored samples from selected read addresses; clocking signal generating means for generating a clock signal at said sampling frequency and N latch signals each having a latch frequency equal to 1/N times said sampling frequency, each successive latch signal being phase shifted relative to a next previous latch signal by a delay equal to one period of said sampling frequency; address control means for generating said selected write addresses and said selected read addresses in response to said clock signal to cause cyclically sequential read out of said N sections such that said stored samples are read out in the order of entry starting from a foremost sample in each of said N sections; and N latch means responsive to respective ones of said N latch signals for latching the read out samples, said selected write addresses and said selected read addresses being generated such that the samples latched by each of said latch means are the samples within a respective one of said N sections and correspond to the respective defined area of the image, outputs of said latch means respectively constituting said N channel signals.