Abstract A noise elimination circuit for eliminating noise signals from data given by a binary form includes a modulo in up/down counter having a first input for receiving binary data, a second input for receiving clock pulses and output for producing a counted signal. The counter is effected to count up in response to the clock pulses when the binary data is a HIGH, and to count down in response to said clock pulses when the binary data is a LOW. A decoder is provided which has inputs for receiving the counted signal, a first output for producing an indication signal when the counted signal corresponds to a first predetermined number i, and a second output for producing an indication signal when the counted signal corresponds to a second predetermined number j, in which i is equal to or greater than zero, j is greater than i and n is equal to or greater than j. A flip-flop is provided which has a reset terminal connected to the first output of the decoder, a set terminal connected to the second output of the decoder and an output for producing a data with noise signals being eliminated.
Inventors
👤 Kenji Toyonaga
👤 Yoshihito Higashitsutsumi
👤 Akihiro Yanai
👤 Toru Akiyama
Bibliographic Details
Application Number—
JurisdictionUS
Data Sourcegoogle_patents
Last Synchronized2026-11-02 16:41
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/125; H03K5/1252
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
255 words
A noise elimination circuit for eliminating noise signals from data given by a binary form comprising: a modulo n up/down counter having a first input for receiving binary data, a second input for receiving clock pulses and output for producing a counted signal, said counter being effected to count up in response to said clock pulses when said binary data is in a first state, and to count down in response to said clock pulses when said binary data is in a second state; a decoder having inputs for receiving said counted signal, a first output for producing an indication signal when said counted signal corresponds to a first predetermined number i, and a second output for producing an indication signal when said counted signal corresponds to a second predetermined number j, said numbers having a relationship n≧j>i≧0; a flip-flop having a reset terminal connected to said first output of said decoder, a set terminal connected to said second output of said decoder and an output for producing a data with noise signals being eliminated; and a detection circuit for detecting a change of number of binary data in the one state contained in a predetermined number of bits, said detection circuit being coupled to said up/down counter such that an up count is effected when said detection circuit detects that the number of binary data in the one state has increased and a down count is effected when said detection circuit detects that the number of binary data in the one state has decreased.
Claim 2
Dependent Claim
255 words
A noise elimination circuit for eliminating noise signals from data given by a binary form comprising: a modulo n up/down counter having a first input for receiving binary data, a second input for receiving clock pulses and output for producing a counted signal, said counter being effected to count up in response to said clock pulses when said binary data is in a first state, and to count down in response to said clock pulses when said binary data is in a second state; a decoder having inputs for receiving said counted signal, a first output for producing an indication signal when said counted signal corresponds to a first predetermined number i, and a second output for producing an indication signal when said counted signal corresponds to a second predetermined number j, said numbers having a relationship n≧j>i≧0; a flip-flop having a reset terminal connected to said first output of said decoder, a set terminal connected to said second output of said decoder and an output for producing a data with noise signals being eliminated; and a detection circuit for detecting a change of number of binary data in the one state contained in a predetermined number of bits, said detection circuit being coupled to said up/down counter such that an up count is effected when said detection circuit detects that the number of binary data in the one state has increased and a down count is effected when said detection circuit detects that the number of binary data in the one state has decreased.
Claim 3
Dependent Claim
14 words
A noise elimination circuit as claimed in claim 1, wherein said relationship is n≧j>n/2>i≧0.
Claim 4
Dependent Claim
44 words
A noise elimination circuit as claimed in claim 1, wherein said detection circuit comprises an m-bit shift register having m cells, an EXCLUSIVE OR gate for receiving binary signals from any two cells of said register, an AND gate for gating said clock pulses.